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Jun 4th, 2013
GLOBALFOUNDRIES introduces certified design flows for multi-die integration using 2.5D IC technology
GLOBALFOUNDRIES plans to unveil a comprehensive set of certified design flows to support 2.5D IC product development with its most advanced manufacturing processes at next week’s 50th Design Automation Conference (DAC) in Austin, Texas.
The sign-off ready flows, jointly developed with the leading EDA providers, offer robust support for implementing designs using sophisticated multi-die packaging techniques, leveraging through-silicon vias (TSVs) in 2.5D silicon interposers and new bonding approaches. Multi-vendor support is available, with full implementation flows from Synopsys and Cadence Design Systems. Physical verification with Mentor Graphics’ suite of tools is included in the flow.
The flows come with a CPU core and memory IP and all the scripts and settings to execute a Synopsys Galaxy™ Implementation Platform-based flow or Cadence Encounter®-based implementation flows with the GLOBALFOUNDRIES PDK. Similarly, the Mentor Calibre® 3DSTACK tool is exercised in the flow to verify DRC, LVS and extraction within and between the various die stacks leveraging the same golden design kits as used inside of GLOBALFOUNDRIES .
Comprehensive design support
The flows provide support for a complete 2.5D design flow. This includes RDL routing between chips on interposer and RDL routing to IO pads. The flows demonstrate all the steps involved in chip pad setup, C4 and microbump placement, and TSV alignment. Designers can use the flows to be guided through processes such as creating top die (logic and memory) with microbumps, followed by interposer creation – including floor planning, microbump, TSV and C4 Bump placement, power mesh generation and signal routing.
The flow incorporates the Cadence 3D-IC solution, which supports all three driving design methodologies: package driven, SoC driven, and custom driven. The solution has been proven on a number of designs ranging from 2.5D to full 3D. All of the requisite technology features are supported and accessible across environments to help unify the design, analysis and signoff tasks on the multiple die and substrate. The Cadence 3D-IC solution includes the Encounter Digital Implementation System with a 3D option.
The Synopsys Galaxy Implementation Platform has been enhanced specifically to address 2.5D design. Designers can implement the Synopsys IC Compiler™ tool for placement, assignment and routing of microbump, TSV, probe-pad and C4; microbump alignment checks; RDL and signal routing, and power mesh creation on silicon interposer interconnection layers. Advanced verification and analysis support is also available for layout vs. schematic (LVS) connectivity and design rule checking (DRC) between stacked die; parasitic extraction for TSV, microbump, RDL; signal routing metal for stacked die and silicon interposer design interconnection; and timing analysis of multi-die systems.
The flows allow for interposer and top-die physical/logical interface and alignment checks at various stages in the design phase. Mentor’s Calibre can be used to verify physical offset, rotation, and scaling at die interfaces. The Calibre 3DSTACK product also enables connectivity tracing and extraction of interface parasitic elements needed for multi-die performance simulation.
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