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Apr 12th, 2012
Georgia Tech proposes industry consortium on Advanced Packaging technologies and heterogeneous 3D integration
For ultra-miniaturized 3D heterogeneous, RF, digital and power modules in partnership with Global companies.
Georgia Tech Packaging Research Center (GT-PRC), through an industry consortium of about ~15 semiconductor, package and supply-chain companies from thd US, Europe and Asia, has been pioneering ultra-miniaturized electronics by Embedded MEMS, Actives and Passives (EMAP) Technology with chip-last (CL) interconnections but with chip-first benefits to demonstrate ultra-miniaturized modules with digital, RF, analog, MEMS and sensor functions. GT-PRC has demonstrated groundbreaking technologies that include ultra-thin organic substrates, fine-pitch Cu-to-Cu interconnections, low temperature bonding with high assembly throughput and prototype functional module demonstration of digital Si and RF GaAs die embedding.
GT-PRC proposes the next consortium, building upon the above advances, 3D ThinPack with a focus on:
The primary objective of the proposed 3D ThinPack consortium is to achieve ultra-miniaturized heterogeneous sub-systems by 3D integration of multiple ultra-slim packages with embedded thin active or passive components. The two-year goal is to demonstrate a four-package stack within ~1mm thickness by advancing the above five technologies shown in Fig 1.
Proposed technologies for ultra-miniaturized 3D stacked modules
The proposed 3D ThinPack research addresses the need for highly-miniaturized and highly-functional heterogeneous modules with particular focus on:
Companies interested in this new consortium are encouraged to contact Mr. Nitesh Kumbhat at email@example.com, 404 385-0730 or Prof. Rao Tummala at firstname.lastname@example.org, 404 894-9097.
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