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Home  >  ADVANCED PACKAGING: 3D IC, WLP & TSV  > HD MicroSystems introduces ultra-low cure dielectric for ...
  >  ADVANCED PACKAGING: 3D IC, WLP & TSV
May 22nd, 2009
 
HD MicroSystems introduces ultra-low cure dielectric for Fan-Out WLP applications
 
HD MicroSystems, a joint venture between Hitachi Chemical and DuPont Electronic Technologies, introduced HD-8930 ultra-low cure polybenzoxazole (PBO), a dielectric layer for fan out WLP and other semiconductor packaging applications that benefit from lower temperature processing. New PBO Enables Fan Out Designs & Superior Drop Test Results for Portable Devices.
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Examples of Wafer Level – Chip Scale Packaging (WL-CSP) with Redistribution Layers (RDL)
Examples of Wafer Level – Chip Scale Packaging (WL-CSP) with Redistribution Layers (RDL)
The new offering is the latest in the HD-8900 low-cure PBO series and combines the proven reliability of HD MicroSystems’ PBO technology with curing temperatures as low as 200°C.  With its low modulus and high elongation, HD-8930 achieves superior drop test results, making it ideal for use in portable electronic devices.

“HD MicroSystems HD-8930 sets a new standard for reliability and performance even in the most challenging semiconductor packaging designs,
” said John Malloy, business manager -- HD MicroSystems.  “We broke the 235°C barrier with the introduction of HD-8910 in 2007, and we’ve continued to drive down the required curing temperatures.  HD-8930 maintains the chemical resistance, thermal and mechanical properties of traditional HD Microsystems’ PBOs while processing at lower temperatures.  This breakthrough enables next generation packaging technologies that require lower device stress and reduced thermal budgets.  This is the type of innovation our customers have come to expect from HD Microsystems, a long time leader in high reliability liquid polyimide technology.”

HD-8930 was developed to bring the highly desirable properties of polyimides and PBOs to lower temperature applications.  It provides another option for chip designers who must meet both increasing chip density challenges and device reliability demands.

HD-8930 is available for sampling late third quarter this year and will be featured at the 2009 Electronic Components & Technology Conference (ECTC), May 26-29, 2009, in San Diego, as part of the broad and growing portfolio of materials represented by DuPont Wafer Level Packaging Solutions.

 
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