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Jul 4th, 2012
 
Hybrid Memory Cube architecture: a closer look
 
At the recent VLSI conference in Hawaii, Joe Jeddeloh of Micron revealed further details about the Micron Hybrid Memory Cube. I-Micronews felt it was worth “A Closer Look”.
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Micron Technology has created an industry group to collaborate on the implementation of an open interface specification for a new memory technology called the Hybrid Memory Cube (HMC).

The HMC is a stack of multiple thinned memory die sitting atop a logic chip bonded together using TSV. This greatly increases available DRAM bandwidth by leveraging the large number of I/O pins available through TSVs. The controller layer in the HMC is the key to delivering the performance boost, allowing a higher speed bus from the controller chip to the CPU and the thinned and TSV connected memory layers mean memory can be packed more densely in a given volume. The HMC requires about 10% of the volume of a DDR3 memory module. It is claimed that the technology provides 15X the performance of a DDR3 module, uses 70% less energy per bit than DDR3 and uses 90% less space than today’s RDIMMs (more info here). 

The Micron HMC

The design of HMC involved many Micron engineering teams including DRAM design, logic layer design, packaging, assembly, process R & D and test.  

A standard DRAM building block can be combined with various versions of application specific logic. Each 1 Gb DRAM layer is optimized for concurrency and high bandwidth. The HMC device uses TSV technology and fine pitch copper pillar interconnect.  DRAM logic is off- loaded to a high performance logic die. The logic die, with high performance transistors, is responsible for DRAM sequencing, refresh, data routing, error correction and high speed interconnect to the host.  The use of TSVs enable thousands of connections in the Z direction. The stacking of many, dense DRAMs produces a very high density footprint.  The HMC was constructed with 1866 TSVs on a roughly 60 u pitch. 

The HMC DRAM is a 68 sq mm  50 nm  1Gb die segmented into multiple autonomous partitions. This structure allows greater than 16 concurrent operations per stack. The DRAM is optimized for random transactions typical of multi-core processors.   
Many of the traditional functions found in a DRAM have been moved to the logic layer.  The high speed host interface, data distribution, address/control, refresh control and array repair functions. The DRAM is a slave to the logic layer timing control.  Any host link interface can connect to any local DRAM sequencer.

 
HMC Block Diagram

HMC electrical performance is are compared to other DRAM modules below.

Power and Bandwidth Comparison

Jeddeloh looks to the future and sees DRAM process geometry and cell size shrinking to half the size it is today. This and improved stacking will allow greater density for a given cube bandwidth and area.  He predicts that HMC devices will extend beyond 8GB. The number of TSV connections will double to create a cube capable of  320 GB/s and beyond.

 

 
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