iMicronews thought his presentation was worth A Closer Look.

After 14 years at Samsung , Kim moved to Seoul Semiconductor in 2010 and then Hynix in his current role in 2011.
Kim compares conventional package on package to conventional WB stack to TSV stacking he concludes that while TSV can result in the best electrical performance and density, PoP still offers advantages in yield and cost.

Hynix has been working on stacked memory with TSV for several years. In 2009 they announced their ability to stack NAND flash, in 2010 their prototypes for LPDDR2 and in 2011 their 16 Gb, 8 chip stacked DRAM. 

Comparing temporary bonding technologies for their ease of removal and handling Hynix finds the “tilt” technology ( TMAT/Suss ) as superior in both categories.

Looking at the 3 possible bonding options Kim feels that while W2W shows expected advantages in throughput and therefore cost, it cannot compete with C2C or C2W in terms of yield or accuracy. According to Hynix, C2W shows advantages over C2C in terms of throughput, cost and accuracy.

In terms of underfilling Kim sees NCF (non conductive film) resulting in better throughput and reliability than NCP (non conductive paste). Fee expet capillary underfill (CUF) to be a player in 3D becase of the smaller gaps and the very slow throughput without vacuum assistance.

Kim reports that Hynix has also found that ~ 10% thermal vias in their designs will reduce the memory stack temp from ~ 105-110 C down to ~ 93 C. 

Kim notes that extreme care should be taken during backside processing because a few molecules of copper is all that is needed to kill the memory cells. 

In terms of supply chain management, Kim sees Hynix favoring the open ecosystem where logic and memory prepared with/for TSV from foundries and IDMs going to OSATs for assembly.

In terms of industry product introductions, Kim sees wide IO, low power memory stacks for mobile applications driven by form factor and power in development in 2012 with low production expected early 2013 ramping to volume late 2014. 

This will be closely followed by DRAM on interposer in a 2.5D configuration for graphics applications, driven by bandwidth and capacity with low production expected in 2013 and ramping to HVM early in 2014. 

Next will be DRAM for high performance computing (HPC) driven by bandwidth and capacity with low production expected in 2013, ramping to volume in late 2014.