Wading through the myriad of options

The pros/cons of the various options should be weighed against each other. Furthermore, the design choices will impact the 3D technology requirements. By way of illustration, consider a H264/AVC encoder chip, consisting of 6 very large instruction word cores (VLIWs) that are attached to a two-layer memory hierarchy. Segregating the memory into a dedicated technology layer may significantly reduce manufacturing costs. But the decision which memory to move will influence the final technology complexity. If, for instance, the L2-cache memories and the L1 memories are integrated onto a second layer, very fine TSVs with 1μm pitch will be needed. This imposes very severe constraints to the 3D technology.

System designers should therefore carefully select which 3D technology option best fits their applications needs. They should be able to evaluate the power/performance/cost trade-offs for the various 3D integration scenarios in the early stages of technology development and system design.

Unfortunately, as of today, no practical commercially available solution exists to assess the physical design implications of each option during the system exploration phase. So there is a need for a methodology that supports co-optimization of 3D technology and system design in the early design phase. Such a methodology will be indispensible to steer 3D system design and to steer the 3D technology roadmap.

PathFinding the risks-benefits of 3D technology

To support designers in identifying their technology/design sweetspot, IMEC has created a PathFinding flow and has set up the design rules and models in support of this flow. Path-Finding is the practice of performing virtual chip design in order to co-optimize system design and 3D technology, to estimate the value proposition of a 3D design and to describe its risks-benefits. The results of PathFinding are a set of clear specs for process teams and design teams. The proposed PathFinding flow is divided into three steps: (1) 3D system level design exploration, (2) register transfer level (RTL) elaboration and (3) 3D physical design prototyping.

The main objective of the first step is to provide the refinement of the system architecture based on requirements and taking into account the benefits of the 3D technology. After this step, the designer holds a functional model of the system architecture, various component models at different abstraction levels and rough estimates of the different quality of result (QoR) parameters. Next, in order to bridge the gap between the system level design exploration (step 1, i.e., models at higher abstraction levels), and physical design prototyping (step 3, i.e., models at lower abstraction levels), we need to produce RTL models of system components.

Within PathFinding, we identified different paths that allow moving from the functional level to the physical level. These different paths will lead to the creation of a physical design data base. The third step finally allows easy and fast exploration of the physical design impact of alternative design/technology options on the QoR parameters.

A 3D-stacked DRAM case study

The capabilities of the PathFinding methodology and associated tool chain are validated on a 3D case study. The 3D case is a simplified version of an existing multi-processor system-on-chip (MPSoC), originally designed for low-power, high-performance video encoding applications. The MPSoC can be partitioned into two dies: a logic die, containing different processing cores, communication infrastructure and the DRAM controller; and a memory die, with memory arrays and associated control logic.

The two dies can be integrated in several ways: (1) using a 2D approach, with the two dies being placed side by side in separate packages on a PCB; (2) using a state-of the- art 3D-SIC implementation that makes use of bonding wires between the dies; and (3) using an advanced 3D-SIC implementation based on TSVs. For the latter implementation, in turn, different scenarios exist.

In the various 3D scenarios, the off-chip DRAM memory has been put on top of the processing die. The PathFinding methodology has then been used to assess the QoR aspects for the different integration options. The focus of the exercise was on the interconnection between the logic and the memory die, a part that will most benefit from the 3DSIC technology.

In the system level design exploration phase (step 1), simplified platform models have been used instead of cycle-accurate models of the complete MPSoC. This allowed us to obtain shorter simulation times. An RTL description (step 2) has been generated for the ADRES processors (using the processor template using IMEC tools), the DRAM controller (using existing third party IP) and the AHB bus. Different workspace environments have been created for each implementation scenario using models from step 2. The 3D-TSV scenarios rely on TSV geometrical and electrical models that take into account all the different layers with their geometry and their material properties. The diameter of the TSVs in this investigation is 5μm, with 25μm pitch.

As a result, the QoR parameters (minimal and maximal resistance and capacitance, maximal and total power dissipation, minimal and maximal delay) are obtained for the different implementation scenarios. The demonstration shows how using TSVs as the method of interconnect allow for a factor 10 decrease in power, thereby allowing for an increase in bus-width between microprocessor and memory. This sample design case demonstrates the capabilities of the PathFinding flow to assess the power/performance tradeoffs of various implementation schemes.

For more information, please refer to mstnews 3/09 “PathFinding: A Methodology to Co-optimize System Design and 3D Technology “ by Pol Marchal.