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Jan 8th, 2013
IMECs Marinissen discusses 3DIC wafer testing: A Closer Look
In the pre conference symposium at the recent RTI sponsored 3D Architectures for Semiconductor Integration and Packaging ( 3D ASIP) conference Erik Jan Marinissen of IMEC gave an in depth look at the state of 3D stack testing . i-Micronews felt it was worth “ a closer look”.
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The 3 main questions he asked and then answered were: 
3D Test 
– what to test and when
3D Test Contents
 – do we need new patterns for new defects
3D Test Access
- external test access: wafer probing
- internal test access: design for test (DfT)
Whereas conventional 2D testing involves only two test points, i.e. wafer test and final packaged die test, 3D stacking required consideration of many more test points.

Test flows in a 3DIC stack

The degree of testing has to be looked at as a cost/benefit tradeoff which will look at the yield and the % of the bad product that the testing could have detected.
In terms of test for new intra die defects they looked for new effects induced by 3D processing such as TSV/ubump proximity, wafer thinning and/or thermocompression stacking. They conclude that these effects have structural processing impact not incidental spot defects and thus this is not a testing issue and needs to be handled by design rules such as keep out zones, delay specs, etc. They also conclude that spot defects with new physical root causes will be detected by existing testing protocols.

Fine Pitch uBump Probing
• Pitch Probe Cards vs ubumps
      - Probe card pitch : > 60 um
      - uBump pitch: 40um ---20um ----10um
• Todays industry solution: dedicated probe pads
      - Extra design effort, area and test time
      - Not the real entry/exit point of the functional data
• Fine pitch ubump probing
      - Cascade pyramid rocking beam interposer probes
      - MEMS type vertical probe card
      - Scalable probe pitch (~20um) and force (< 1 gf/tip)

Testing of IMEC standard structures involves 15 um bumps on 40 um pitch and bottom bumps are 25 um on 50 um pitch.

IMEC top and bottom pad dimensions

KGD testing is usually done on dicing frames, but for thinned wafers most probers cannot handle the sagging. Marinissen reveals that TEL now offers automated handling and probing  of 300 mm wafers on dicing frames. 

Probing on a dicing frame

Design for test (DfT) is used for prebond, post bond and  post packaging testing.

Design for test

As an example, Marinissen shows the results of IMEC consortium partner TSMC’s testing of logic + memory structures. 

TSMC Logic + wide IO DRAM Design for Test




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