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Sep 7th, 2012
IMECs Marinissen examines JEDEC wide IO Memory: a closer look
Wide IO memory is thought to be one of the most important advances for moving 3DIC forward towards high volume manufacturing.
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Wide IO memory is thought to be one of the most important advances for moving 3DIC forward towards high volume manufacturing (see the related articles here: www.i-micronews.com/news/Samsung-Wide-IO-Memory-Mobile-Products-Deeper-Look,6503.html and www.i-micronews.com/news/Update-JEDEC-wide-I-O-standard-3D-ICs,8060.html).

IMECs Erik Jan Marinissen, expert in all things 3DIC Test, and co-workers  from Cadence recently wrote an interesting article on the status of “Interconnect Test for Wide-IO Memory-on-Logic Stacks” for Future Fab Int.
Read the article here

iMicronews thought this publication deserved  “A Closer Look”…..

JEDEC standard, JESD-229 ,  for stackable Wide-IO DRAMs widens the conventional 32-bit DRAM interface to 512 bits offering more bandwidth at lower power. The standard defines the functional and mechanical aspects of the wide-IO logic-memory interface including the electrical specification, usage protocols and ball-out.

JEDEC’s wide-IO logic memory interface defines four independent memory channels (a, b, c and d) of 128 bidirectional DQ data bits each, totaling 512 data bits over all four channels. The maximum data rate is 266 Mbps which offers a total logic-memory bandwidth of 17 GBs. Each channel includes independent control and clock, and shared power and ground.

The mechanical aspects of the standard include the pad locations, dimensions and tolerances. The interface consists of 300 micro-bump pads per channel, making 1,200 connections for all four channels. Each channel consists of six rows by 50 columns of (micro-bump) pads at a pitch of 40 μm in the short axis and 50 μm in the long axis.

The wide-IO interface allows for stacking of up to four DRAM dies on top of each other.

Such a four-rank stack consists of 16 memory blocks, of which only four blocks (i.e., one per channel) can be accessed at a time. The JEDEC wide-IO DRAM allows for a variety of stack configurations; the industry has reported on prototype chips where a logic die and a stack of four wide-IO DRAMs are stacked side by side on a passive silicon interposer, as well as on a single-tower 3D-SIC consisting of two logic dies and a single wide-IO DRA.




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