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> Imec and Synopsys collaborate on 3D stacked IC development...
> ADVANCED PACKAGING: 3D IC, WLP & TSV
Mar 10th, 2010
Imec and Synopsys collaborate on 3D stacked IC development
Synopsys, Inc., a world leader in software and IP for semiconductor design, verification and manufacturing, and the Belgian nanoelectronics research center, imec, announced they have entered into a collaboration to use Synopsys TCAD (Technology Computer-Aided Design) finite-element method tools for characterizing and optimizing the reliability and electrical performance of through-silicon vias (TSVs). The collaboration will accelerate the development of 3D stacked IC technologies.
While considered an emerging technology, 3D stacked IC complements conventional transistor scaling and allows multiple chips to be stacked and integrated into a single package. This technology reduces form factor and power consumption, and increases bandwidth of inter-chip communication by minimizing connections through the circuit board with high parasitic capacitance. As with other innovative technologies, 3D stacked IC introduces a number of new issues that can potentially affect its reliability and performance. The collaborative research to address these issues will take place at imec, where silicon wafers with test structures will be manufactured and tested, and Synopsys' TCAD tools will be used to model the TSVs in the chip stacks to optimize 3D stacked IC performance and reliability. Sources :
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