At the recent European microelectronics packaging conf. in Grenoble Fr. LaManna, Beyne and co-workers from IMEC reported on electrical characterizations done to identify the impact of typical 3D processes on CMOS devices. I-Micronews felt this work was worth…a closer look.
To characterize the process steps of interest, they use dedicated test structures that are measured before and after the process. The results reported in this work are for process flows using D2D stacking with thin wafer de-bonded and diced after back-side processing.
They report on the study done to assess the effects induced by TSV, wafer thinning, micro-bump, and stacking.
Stress induced by TSV
During the thermal process steps in a 3D process flow, the CTE difference between Cu and Si induces mechanical stress in the proximity of Si and TSV. A tangential compressive stress is built-in during Cu annealing process while radial tensile stress is built-in after TSV cooling down due to the shrinkage of Cu. To study the effect of mechanical stress induced by TSVs on MOSFET devices, they examined two sets of FET arrays for each FET dimension: a) test array - FET matrix with TSV and b) reference array -same FET matrix without TSV.
Measured ION variation as a function of TSV proximity for PFET and NFET transistors.
PFET values reported for channel lengths of 50nm and 300nm; NFET values reported
for channel lengths of 70 and 320nm.
The Figure shows measurements done for PFET transistors ( 2 channel lengths (50nm and 300nm) with TSV of 5um diameter). They conclude that the longer channel is more sensitive to TSV presence, i.e. at a distance of 5um from TSV center, they measure ION variation of 7% in the case of 300nm channel and 2.5% variation in case of 50nm channel. NFET transistors are less sensitive to TSV proximity. At a distance of 5um from TSV center, they measure a max ION variation of 2.5%. Similar to PFET, NFET transistors with longer channels are also more sensitive to TSV proximity.
The measurements illustrated in the figure below confirm the different sensitivity based on channel length: transistors with longer channel are more sensitive.
Measured ION variation as a function of TSV proximity for PFET transistors of varying channel length.
Stress induced by wafer thinning
During the thinning process, the wafers are processed through several mechanical and chemical steps.
The IMEC group measured the ION variation before and after thinning. After thinning the wafer was processed with SiN back side passivation. The final wafer thickness is ~50um. Prior to testing the wafer was de-bonded and transferred to dicing tape.
The ION current was measured on FET arrays with and without TSV for PFET and NFET with channel width and length of 500nm and 70nm respectively. The results for the PFET arrays (demonstrated as most sensitive) with TSV are shown in the figure below. Results show no relevant change in the device drive current and therefore no major effect induced by the thinning process.
Stress induced by 3D stacking
The process of 3D stacking is done by thermo-compression bonding using a die-to-die (D2D) approach. The use of underfill, typically pre-applied, is required to improve stack reliability . The stress induced by the stack process, the presence of micro-bump and the eventual underfill shrinkage could affect device performance.
Testing consisted of measuring the ION current for PFET and NFET arrays, with and without TSV. The wafer had been processed through thinning, back-side passivation, micro-bumping, de-bonding and finally diced.
They report the measurements done on the PFET and NFET arrays with TSV by comparing the ION before thinning and after stacking. No major variations are observed.
ION measurements in case of PFET and NFET arrays with TSV, before thinning and after stacking.
In summary they conclude:
• PFET devices are more sensitive to TSV-induced stress than NFET
• Transistors with longer channel are more sensitive
• Wafer thinning and die stacking do not show any relevant effect on ION variation.