Home  >  ADVANCED PACKAGING  > The Intel “Tri-Gate Transistor” structure: a closer look...
Oct 4th, 2011
The Intel “Tri-Gate Transistor” structure: a closer look
At the most recent Intel developer forum, Intel Sr Fellow Mark Bohr gave a presentation “ 22 nm Tri-Gate Transistors for Industry Leading Low Power Capabilities”, detailing their “3D” tri-gate transistor technology also known as “finfet”.
Send to a friend

Intel first announced this new technology in May [see “Intel Readies 22nm Leap, with Trigates”]. The first tri-gate-based processor, “Ivy Bridge,” is slated for high-volume production by the end of this year. It is likely that these new structures will be at the leading edge of future packaging needs and will be the designs that will be stacked in 3D so i-Micronews felt the technology deserved “A Closer Look”.

Many of us recall Bohr from 1995 when he predicted  that Al and SiO2 interconnect  would soon ( post 0.35 µm) be the bottleneck for chip performance. (see below). This prediction proved to be highly accurate as we soon moved to industry adoption of Cu interconnect and  the still continuing “holy grail” search for Lower-K dielectrics. 

Bohr’s prediction that Interconnect would dominate timing delay post 0.25 micron

With leakage increasing orders of magnitude due to gate oxide thickness reduction, Bohr contends that traditional CMOS scaling began running out of steam in the early 2000’s.

Impact of gate oxide thickness on Leakage

Scaling continued to move forward by materials changes such as strained silicon and high K gate oxides. 

 Strained silicon and high K gate oxide enter the scaling roadmap

In order to continue moving forward at 22 nm Intel has moved to what they call  3-D Tri-gate transistors where the gate is formed on 3 sides of the conducting channel which is now a silicon “fin”. Multiple fins can be used for higher drive current and higher performance.

 Planar transistor structure vs single and multifin “Tri-gate” transistors

These tri gate transistors result in lower leakage current and lower operating power. This results in a 37% delay improvement at lower voltages. 

Lower leakage and lower gate delay from Tri-gate transistors

Concluding that planar transistors cannot provide expected performance and power reduction improvements at 22 nm, Intel contends that 22 nm tri-gate technology can deliver:
-  37% performance increase at low voltage
-  50% power reduction at constant performance
-  Adds 2-3% wafer cost compared to 22 nm planar technology.
The chart below proposes that others will follow Intel’s lead in a few years  as they have in strained silicon and high K metal gate technology.

Intel contends that others are 3-4 years behind in transistor developments

Below is Intel’s assessment of market impact in the various market segments.

Impact of performance, power and leakage on market applications

Mark Bohr - Intel Sr Fellow



Sep 17th
Sep 11th
Sep 11th
Sep 11th
Sep 11th
©2007 Yole Developpement All rights reserved                  Disclaimer | Legal notice | To advertise
Yole Développement: Le Quartz, 75 cours Emile Zola, 69100 Villeurbanne, France. TEL: (33) 472 83 01 80 FAX: (33) 472 83 01 83 E-Mail: info @yole.fr