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Jun 30th, 2014
Intel Knights Landing: A closer look
At the 2014 International Supercomputing Conf. in Leipzig Germany last week Intel revealed details of their new second generation Xenon Phi processor “Knights Landing” and Micron announced an ongoing collaboration with Intel to deliver a TSV based “on-package memory” solution. i-Micronews thought these announcements were worth… A closer look.
At the 2014 International Supercomputing Conf. in Leipzig Germany last week Intel revealed details of their new second generation Xenon Phi processor “Knights Landing” and Micron announced an ongoing collaboration with Intel to deliver a TSV based “on-package memory” solution. Knights Landing [KNL] is the code name for the second generation Intel “Many Integrated Core” (MIC) architecture which will debut in 2015 and be used in high performance computing [HPC] (more).
Intel XenonTM Processor Roadmap
KNL will be manufactured by Intel using 14nm FinFET process technology and will include up to 72 processor cores that can operate with up to four threads per core. Intel has disclosed that this chip will be based on a version of the Silvermont core used in Intel's Atom processors and support for up to 384 GB of DDR4 RAM and 16GB of 3D stacked DRAM on-package ( Micron Hybrid Memory Cube, HMC), providing up to 500GB/sec of memory bandwidth. It will be the first Intel HPC processor to use 3D stacked memory.
KNL Xeon Phi has a 6-channel DDR4 memory controller supporting up to 384 GB RAM per socket. The stacked 3D memory or multi channel DRAM (MCDRAM) in the CPU package has a customized memory interface. It is expected to deliver 5X the memory bandwidth versus GDDR5 with 1/3 the energy per bit in half the footprint. ,
KNL 3D Stacked HMC DRAM in CPU Package with DDR4 on Motherboard (source: VR-zone) (more).
KNL architecture is shown below:
Knights Landing Processor Architecture [source: VR-zone] (more)
Knights Landing is expected to be deployed in the Cray “Cori” at National Energy Research Scientific Computing (NERSC) Center (more). It has been reported that the “Cori” will use over 9,300 Knights Landing nodes each of which uses eight HMCs, with each HMC built using four DRAM chips and one logic chip, totaling about 300,000 DRAM chips for the single system (more).
Micron and Intel have been collaborating on this program for years. Intel first revealed of the memory cube technology at their Intel Developers Forum in June of 2011 (more).
HMC Presented at IDF 2011 [source: Micron]
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