Micron recently announced that it is shipping 2GB Hybrid Memory Cube (HMC) engineering samples. i-micronews had a chance to discuss HMC activities with Microns Mike Black and Susan Platt and thought the information was worth… a closer look.
In October 2011, Micron and Samsung formed the hybrid memory cube consortium to develop industry standards in order to integrate the HMC into a wide variety of systems (more).
This is the first time that memory leaders Micron, Samsung, and SK Hynix have teamed up for such a joint effort. Consortium developers include (Altera, ARM, , IBM, Micron, , Open-Silicon, Samsung, SK Hynix, and Xilinx). Although expected customers like Intel and AMD are not consortium members, it is generally thought that they opted not to be involved in the open standard in order to develop their own way of using the technology. Intel demonstrated a prototype HMC device during the fall Intel Developer Forum in September 2011, deeming it the fastest and most efficient DRAM ever built (more).
The Hybrid Memory Cube (HMC) is a new memory architecture that combines a high-speed logic layer with a stack of through-silicon-via (TSV) bonded memory die. Reportedly, a single HMC offers a 15x performance increase and uses up to 70 percent less energy per bit when compared to DDR3 memory, and takes up to 90 percent less space than today's RDIMMs.
As microprocessor speeds exceeded DRAM memory speeds, a bottleneck developed that is referred to as the memory wall. HMC, however, enables higher memory bandwidth. Utilizing wider arrays of TSV’s in the memory stack, each DRAM layer can be accessed to provide more memory responders or banks available to the system. As a result, the controller can simultaneously access much more bandwidth than could be accomplished with a standard DIMM package. System latency is also greatly improved through the stacked memory solution as a result of many banks operating in parallel.
Micron’s initial HMC (shown below) features a 2GB memory cube that is composed of a stack of four 4Gb DRAM die. The solution provides 160 GB/s of memory bandwidth while reportedly using up to 70 percent less energy per bit than existing technologies.
The 2 GB Micron HMC
Details on the 2GB HMC
The logic layer, containing the control functions, is being made on 300mm wafers by IBM using their 32nm technology, the memory layers in 30nm DRAM technology are manufactured at Micron DRAM sites and both are shipped to Microns Boise site for assembly.
The memory layers are thinned to 50um and assembled with 20um high Cu pillar technology. Although TSV size has not been revealed, the cross section of the stack (first shown at the 2012 VLSI conference in Hawaii) indicates 6-7um TSV (more). Micron is also remaining vague about the number of connections (TSV) per layer although we do know that the memory array is broken into 16 partitions and each partition has several thousand TSV per layer. C5 pitch (BGA balls) appears to be standard 1 mm.
The logic die is being assembled to the BGA substrate then the memory layers are stacked on top.
Micron 2Gb HMC
Are TSV taking up space?
Platt indicates that removal of the controllers to the logic layer and addition of the required TSV results in chips that are approximately the same size as expected DDR4 devices where the controllers cannot be removed.
Although customers cannot yet be identified, initial applications appear to be high-speed networking and high performance computing (HPC). Black noted that today’s routers operate at 100G line rates but that they are moving soon to 200G and then 400G. Black feels that “DDR4 just will not be able to handle this move.”
Platt adds that “Eventually, due to energy and bandwidth requirements, HMC will drive exascale CPU system performance growth for next generation HPC systems."
At the recent Semicon Taiwan Micron presented the following technology comparison of HMC to DDR3L-1600 and DDR4-3200 in terms of what it takes to support 1.28TB/s of performance?
Supporting 1.28TB/s of performance: Comparing HMC to DDR3L-1600 and DDR4-3200
Consortium standardization efforts
The consortium introduced HMC interface and protocol specification in April 2013. The specification provides a short-reach (SR), and an ultra short-reach (USR) interconnection across physical layers (PHYs) for applications requiring tightly coupled or close proximity memory support for FPGAs, ASICs and ASSPs, such as high-performance networking and computing along with test and measurement equipment.
Platt indicates that “…the next goal for the consortium is to develop a second set of standards designed to increase data rate speeds. This next specification, which is expected to gain consortium agreement by 1Q14, shows SR speeds improving from 15 Gb/s to 30 Gb/s and USR interconnection speeds increasing from 10 to 15Gb/s.”
Micron expects 4GB HMC engineering samples to be available in early 2014 with volume production of both the 2GB and 4GB (which will contain 8 memory layers) HMC devices beginning later in 2014.