NANIUM earlier this year licensed Flip Chip International’s (FCI) Spheron® Plated Cu Redistribution technology to provide solutions for 300mm wafer-level chip scale packaging (WLCSP) using fan-in WLP processes. After completing line setup and qualification for that technology, the company added the capability to manufacture fan-in WLP products, which extends its service portfolio using the latest technology on 300mm wafers.
 
“The conventional fan-in variant of WLP on the silicon wafer, where all IOs are located on the die, offers a cost-effective solution for the required package size, IO count and performance of many ICproducts,” said Armando Tavares, president of NANIUM’s executive board. “By leveraging our proven WLP processes and know-how, NANIUM is now extending its service offer to cover the full range of wafer-levelpackaging requests of our customers, fan-in and fan-out.”
 
Wafer-level chip scale packaging (fan-in WLCSP) enables low-cost manufacturing of small die sizes, with low I/O density, and high performance. The technology includes repassivation, redistribution (RDL), under-bump metallization (UBM), bumping, test, laser marking, singulation, automatic inspection (AOI) and pick and pack in tape and reel.
 
This technology complements NANIUM’s existing fan-out WLP offer, which is more directed to high-pin / high-performance products, SiPs and 3D integration.

NANIUM recently passed the production milestone of 200 million components using embedded wafer-level ball grid array (eWLB), a fan-out WLP technology.