Bringing turnkey CMOS manufacturing benefits to MEMS designers, by Martin Lim.
The highly recognized success of the fabless semiconductor industry has stemmed from process standardization. Rapid innovation, a wide array of products and efficient manufacturing have led to low-cost and innovative products suitable for mass adoption in high-volume markets such as consumer electronics. Paving the way is the standardization of CMOS processes, where foundries can provide fabrication services to fabless design companies. Rapid development times based on well-developed design infrastructure and tools are further supported by low-cost manufacturing and virtually inexhaustible capacity. In addition, the standardization of semiconductors has triggered economies of scale for both packaging and test, which translate into a lower cost of finished products.
In order for the MEMS industry to replicate the success of the CMOS fabless model, there is a need for a similar standardized process technology. This will ultimately lead to the proliferation of disruptive MEMS-based solutions for a plethora of applications including motion sensing, navigation for location-based services, wireless communications, health and environmental sensing and many others.
This paper will describe the challenges for MEMS standardization, and introduce the patented Nasiri-Fabrication (NF) Platform as the most effective way to overcome them. The NF Platform is a versatile process that can support multiple products, addresses all cost contributions, and is already deployed at the top 2 tier-1 CMOS foundries. Attributes of the NF Platform and its ultimate benefits will be highlighted in this paper.
Challenges to MEMS Standardization
The fundamental challenge for MEMS technology is the availability of a MEMS process platform that matches the qualities of CMOS process technology. In short, the MEMS platform should effectively address the widely-accepted difficulties for MEMS developers including long and costly custom process development, complicated and sub-optimum electronic integration, custom packaging processes and costly test procedures.
Versatile low cost fabrication platform
MEMS has largely stayed with a one product, one process paradigm. Furthermore, the difficulty and burden of custom-process development for each new device has been a major challenge and hindrance to achieving volume production for many MEMS companies. A few MEMS manufacturers have tried to design products that leverage standard CMOS fabrication lines by bringing select MEMS specific processing steps into the foundry however, most MEMS require unique fabrication development and product-specific parameters that are not transferable to other MEMS products. To become a viable MEMS fabrication platform, processes must meet the fabrication requirements for a very wide array of MEMS products and applications.
Another critical requirement for a standard process is the capability to address the real-cost drivers of every MEMS device – packaging and testing. More often than not for traditional MEMS, the cost of a MEMS product is determined more from the cost of packaging and testing than the MEMS chip itself. In fact, packaging and testing for traditional MEMS devices usually exceed 50% of the total product cost. The key attributes of the NF Platform are the ability to perform electronic integration, wafer-level packaging and wafer-level testing.
Foundries have been rewarded from their commitment to standardize CMOS processes via greater demand for processed wafer products. With one standard process they can serve many customers and provide a lower cost. As the same equipment, process modules, and even manufacturing systems are shared, foundries benefit from economies of scale. The foundries provide stable processes that enable the ability to produce predictable devices which are then packaged to form ubiquitous electronic solutions. The foundries are then capable of focusing on manufacturing efficiencies including yield and equipment utilization to provide cost effective wafer processing for their customers.
One reason the leading CMOS foundries have hesitated to invest in MEMS fabrication is the uncertain return on investment. To realize value, CMOS foundries need to develop a versatile platform. Historically a majority of the successful MEMS products have served the automotive market; a few promising high-volume products, such as accelerometers and microphones have been delivered by independent device manufacturers (IDMs) with in-house capabilities. Fabless MEMS manufacturers, have been searching for ways to make their MEMS more compatible with standard CMOS process lines and realized quickly that specialty processes and associated equipment should be kept at a minimum. The Nasiri Fabrication (NF) Platform addresses this demand as it has enabled CMOS-MEMS integration and demonstrated huge benefits through high-volume penetration in the consumer market. High volume ensures efficient utilization of any dedicated MEMS tools The MEMS process is inherently simple requiring a few additional masking operations to a standard CMOS process. The NF Platform MEMS enhancement can then be viewed as a module similar to high-voltage, mixed-signal, or embedded-memory additions to the baseline process, making it attractive to CMOS foundries as they expand their process offerings.
Nasiri Fabrication Platform – A solution for MEMS standardization
InvenSense’s proprietary NF Platform is a MEMS fabrication process that provides high performance, high volume, and low cost production. In fact, InvenSense has shipped hundreds of millions of MotionTracking devices built on the NF Platform, which is now available to other MEMS developers. The platform is based on integrated CMOS-MEMS as shown in Figure 1. The innovative NF Platform, with years of optimization, has proven to be a highly-reliable, manufacturable, and low-cost process, which is currently in production at leading tier-one semiconductor foundries.
NF Platform integrated CMOS-MEMS device (Courtesy of InvenSense)
The NF Platform provides on-chip MEMS integration with CMOS circuits. The CMOS area for the device can be used for signal conditioning, analog to digital conversion, filtering, or other sophisticated logic including microprocessors, FIFOs, memories and others. MEMS devices built on the NF Platform tend to be highly integrated System On Chip (SOC), or “smart sensors.”
Since the onset at InvenSense, the premise has been to develop the lowest cost MEMS fabrication platform by addressing wafer-level packaging and electronics integration. This is the first MEMS fabrication process that allows for the integration of MEMS and CMOS with no interdependency on either the CMOS technology or MEMS technology. Each wafer is fabricated separately using the appropriate optimized process. The MEMS and CMOS wafers are bonded together using a patented, low-temperature eutectic bonding process. This bond produces wafers with hermetically sealed and electrically interconnected self-contained die that may be treated, processed, and packaged like standard CMOS wafers (Figure 2). Resulting devices can now be packaged in any standard semiconductor package, including the smallest and lowest cost Quad Flat No lead (QFN) package.
Cross section of die through NF Platform wafer-level CMOS-MEMS integratio (Courtesy of InvenSense)
This process has been used to manufacture single (1) - to six (6)-axis Motion Tracking devices comprised of gyroscopes, accelerometers and other location-sensing elements. The NF Platform can also be leveraged for pressure sensors, compasses, microphones, resonators and a myriad of other MEMS products.
NF Platform – Process overview
The fundamental attributes of the NF Platform are its simple MEMS process and its seamless integration with CMOS. Nasiri-Fabrication uses single crystal bulk silicon and represents the latest evolution in MEMS fabrication. The process outlined below (Figure 3) uses five simple mask levels with only one critical mask level to define the device layer. Manufacturing uses standard off-the-shelf processes and commercially-available equipment.
The engineered Silicon On Insulator (ESOI) wafer (Figure 3a) is formed using a standard silicon handle wafer with simple etched targets for backside alignment followed by a cavity etch and oxidation. A second wafer is fusion bonded to the handle wafer and subsequently thinned to define the device layer thickness. The device layer is then patterned with standoffs to define a hermetically sealed ring and electrical contacts to CMOS. A germanium based layer is then formed over the standoffs. The MEMS wafer is then completed (Figure 3b) by patterning and deep reactive ion etching the device layer to form the mechanical structure.
Nasiri Fabrication Process Flow (Courtesy of InvenSense)
A completed standard CMOS wafer (Figure 3c) developed and fabricated from standardized processes, comprise the second component of the CMOS-MEMS wafer integration. The top aluminum of the CMOS serves as wire bond pads, hermetic sealing ring, electrical contacts to MEMS, and electrodes interfacing to the MEMS structure. The MEMS wafer is bonded to the CMOS wafer using AlGe eutectic bonding between the Al on the CMOS and the Ge on the MEMS wafer. After bonding, a portion of the MEMS wafer is removed by conventional tab saw dicing to expose the CMOS wire bond pads.
The final integrated wafer product is a CMOS wafer serving as a base substrate on which MEMS devices have been fabricated on top (Figure 3d). Since each of the individual MEMS has already been hermetically packaged at the wafer level to a corresponding CMOS die, the integrated wafer can leverage the standard semiconductor backend processes including wafer-level testing, singulation, and low cost plastic molded packaging. A cross section of a complete CMOS-MEMS integrated die is shown below.
Cross section of a completed integrated device. Inset is MEMS structure above CMOS layers
NF Platform benefits
The cornerstone of the NF Platform is the integration of CMOS and MEMS at the wafer level. Direct MEMS to CMOS electrical interconnect provides very low parasitic signal coupling and good shielding capability. The CMOS multi-layer metal stack also replaces the traditional MEMS routing approach which is typically limited to a single un-shielded, high-resistance polysilicon layer. Moreover, the close integration with CMOS electronics allows electronic trimming and compensation for any MEMS process variations, thereby relaxing manufacturing tolerances and increasing yield and manufacturability.
The NF Platform has three major benefits leading to successful commercialization; faster development time, low cost, and fast production ramp up. Consequently the benefits are derived from the virtues of the CMOS semiconductor model:
1. Faster development time
As MEMS devices are traditionally “one product, one process,” MEMS processes tend to be proprietary and single purpose. As a result, when a new MEMS product is developed, a higher percentage of the development time and resources is spent on process and productization than on the design optimization. This ultimately leads to a highly customized, non-standard fabrication process that is often unsuitable to transition into higher volume production foundries resulting in higher costs and lower yielding devices.
The versatility and simplicity of the NF Platform enables designers to focus on disruptive designs and applications vs. laboring on costly process development. Developers can readily design using predictable properties of single crystal silicon and interface with necessary electronics to build a complete MEMS system. This electronics integration and the low-cost packaging compatibility are virtually essential for any product introduction. Historically, it has taken twenty five years or more for a MEMS device to mature from initial proof of concept to high-volume production for the consumer market. The NF Platform not only eliminates lengthy process development, but its single-chip solution circumvents any packaging development. In contrast, MEMS to electronics integration traditionally has been done with a two-chip solution.
2. Low cost product
The NF Platform and its inherent wafer-level integration of electronics and hermetic sealing address two major cost components, namely packaging and testing. Since the MEMS structures are hermetically sealed, and therefore protected, with contact pads exposed (Figure 5), the wafer may be treated as a normal CMOS wafer, without the need for special handling during further processing (e.g. dicing or grinding). This aspect is very attractive to high-volume foundries which are often not outfitted with specialized MEMS equipment such as stealth or laser dicers, and allows them to use their standard high throughput equipment and processes. This allows market introduction at the most competitive prices.
The wafer-level encapsulation protects each MEMS component and enables standard backend processes including lowest cost QFN plastic molded packages. Recall that the electronics are already integrated and therefore the package houses a single chip lending itself to the smallest foot print possible. The low cost, small foot print packaging benefit is critical to market adoption. Further cost improvement is achieved through wafer-level testing. The CMOS-MEMS wafer-level integration transforms a traditional MEMS die and supporting CMOS electronics die into an integrated system.
Completed 8” CMOS-MEMS wafer using the NF Platform.
The inset shows a close-up of the die with exposed wire-bond pads (Courtesy of InvenSense)
The wafers can be fully tested using standard high throughput wafer probers (Figure 6), significantly reducing test cost, simplifying yield enhancement, and improving quality by allowing for the packaging of only known good die. In contrast, in traditional MEMS processing, only rudimentary testing can be done on the MEMS-only wafers. Typically, the utility of the MEMS-only test is limited to a crude determination if the device is mechanically compromised. Due to CMOS-MEMS integration and the inherent System On Chip (SOC), a significant amount of functionality and trimming can be accomplished at the wafer level. In addition, this higher level data set can be relayed to the foundry for more effective process feedback. Last, the simplicity attribute of the NF Platform has resulted in the porting of the process to multiple foundries. This has led to further cost reduction due to competitive wafer pricing.
Wafer level probe results showing excellent yield and fallout bins (Courtesy of InvenSense)
3. Fast production ramp and high volume capacity
The entire NF process is CMOS compatible and is sufficiently simple for CMOS manufacturers to embrace. For this reason, it is very attractive to Tier 1 CMOS foundries as a straightforward way to leverage their existing infrastructure and provide a value add to their existing CMOS production. The absolute large volumes reaching many thousands of wafers per month are best served by proven semiconductor foundries rather than boutique MEMS only foundries. The same benefits that these foundries provide to their CMOS users including great process control and yield, high-volume capability, and predictable and reliable delivery, are now provided to their MEMS customers. All the virtues of semiconductor high-volume production are realized where traditional MEMS foundries were challenged. Additionally, these CMOS foundries are expertly equipped in providing stable processes and cost reduction measures. The simplicity of the NF Platform creates minimal overhead to their manufacturing flow and consequently has marginal impact to their manufacturing efficiencies. In fact, the MEMS process component of the manufacturing will enjoy economies of scale due to its consolidation with the CMOS line. By adopting the simple yet versatile NF Platform, the CMOS foundry can support multiple devices, avoid inefficient, underutilized boutique MEMS processes, and thus provide appropriate cost models associated with the NF platform.
NF Platform expansion and availability of NF Shuttle
The NF Platform, based on single crystal silicon and electrostatic transduction, can support a wide range of devices, including inertial sensors, pressure sensors, resonators, and other similar systems. In addition, with simple enhancements, the platform can support a myriad of additional MEMS devices from micro-fluidics to magnetics to acoustics. It is recognized that most MEMS wafers with the addition of Ge deposition can be integrated to CMOS using the platform thus supporting a MEMS system. Currently, the NF Platform is qualified in two tier-one foundries for high-volume production.
The availability of the NF platform to outside users was initially announced with the NF-Shuttle service in May 2012. This effectively launched the standardization of a fabrication process to the MEMS Industry. The NF-Shuttle apportions costs amongst multiple users as they can purchase "seats" on the same mask set. This approach reduces upfront development costs for participants to a fraction of the total, providing a greater opportunity to verify advanced designs and prototypes in silicon. The designs are run on multi-user wafers using the NF Platform at the same foundries used for InvenSense production, thereby assuring users that their designs will run on a stable and reliable process every time. The NF-Shuttle is a multi-project shuttle service that is open to qualified MEMS device developers from commercial companies as well as from the research community. For the MEMS industry, the NF-Shuttle opens the opportunity for bringing additional MEMS innovations to the market at increased speed due to shorter development cycles and lower development costs.
Interested companies and research institutes are encouraged to contact InvenSense as soon as possible to secure their seat in the next available NF-Shuttle. This will reduce the risk of non-availability and prevent waiting for the next available shuttle run. The next shuttle tape-out is in December, 2012. The following shuttle is scheduled for April 2013 with a plan to launch a new shuttle run every four to five months.
For more information, please visit the NF Shuttle website at www.invensense.com/nfshuttle, or contact InvenSense by e-mail at firstname.lastname@example.org