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Feb 27th, 2012
NUF underfill limiting chip thinning: a closer look
A recent report by IMEC at the IEEE 3DIC in Japan focused on the Si stresses in 3D stacked ICs caused by the thermo-mechanical interaction of the underfill, microbumps and Silicon die.
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130 nm test structures were built on a 200 mm wafers with 5.2 um (5:1 AR ) Cu TSVs. The die was thinned to 25 um and bonded to another die with 30 um diameter Cu/Sn microbumps at 250 C. The gap between the microbumps was filled with NUF. FEM was used to determine key stress generation contributors.

The underfiller (unfilled NUF ) has the highest CTE in the stack. The 25 um thick die upon cooling of the stack from reflow or thermocompression bonding shows local curvature at the microbump position due to shrinkage in the underfill . Bending of the thin silicon causes biaxial in plane tension over the microbumps and biaxial in plane compression in the valleys. 

Silicon deformations above microbump arrays (25 um silicon) (protrusion exaggerated)

Electrical measurements and FEM models both show ~ 40% deviation in electrical data from transistors directly above the underfilled microbump areas.

Characterizing Underfill-microbump induced stress in Silicon; FEM model vs electrical measurements

Stress data for 8 different materials are compared in the figure below which shows a 4X range of stress is achieved as the CTE changes from ~ 25 to ~ 75 ppm. Increasing the filler content lowers the CTE but raises the Youngs Modulus (stiffness) . The CTE has a more dominant impact than the Youngs Modulus. 

Stress vs CTE for 8 diff Underfill Samples

Increasing the SI thickness from 25 to 50 um reduces stress levels 3X . Changing the microbump pitch results in a stress reduction as well (from 200x200 to 50x50 resulted in 2.5X lower stress for the 25um thick Si. It is reasoned that the lower stress is due to the smaller amount of underfill between the bumps.

It has been widely accepted that lowest cost of ownership and best electrical and mechanical results are achieved when the smallest diameter, lowest AR TSV possible are used.  Current results clearly indicate that Si thickness of 25 um requires careful selection of underfill properties and bump array pitch so as not to adversely  impact electrical performance. Wafer level underfill (WUF) which is filler and thus has a lower CTE should be looked at as a solution to this issue.



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