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Feb 27th, 2012
NUF underfill limiting chip thinning: a closer look
A recent report by IMEC at the IEEE 3DIC in Japan focused on the Si stresses in 3D stacked ICs caused by the thermo-mechanical interaction of the underfill, microbumps and Silicon die.
130 nm test structures were built on a 200 mm wafers with 5.2 um (5:1 AR ) Cu TSVs. The die was thinned to 25 um and bonded to another die with 30 um diameter Cu/Sn microbumps at 250 C. The gap between the microbumps was filled with NUF. FEM was used to determine key stress generation contributors.
Silicon deformations above microbump arrays (25 um silicon) (protrusion exaggerated)
Characterizing Underfill-microbump induced stress in Silicon; FEM model vs electrical measurements
Stress data for 8 different materials are compared in the figure below which shows a 4X range of stress is achieved as the CTE changes from ~ 25 to ~ 75 ppm. Increasing the filler content lowers the CTE but raises the Youngs Modulus (stiffness) . The CTE has a more dominant impact than the Youngs Modulus.
Stress vs CTE for 8 diff Underfill Samples
Increasing the SI thickness from 25 to 50 um reduces stress levels 3X . Changing the microbump pitch results in a stress reduction as well (from 200x200 to 50x50 resulted in 2.5X lower stress for the 25um thick Si. It is reasoned that the lower stress is due to the smaller amount of underfill between the bumps.
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