Home  >  ADVANCED PACKAGING  > Nvidia R&D chief sketches road to chip stacks...
Apr 2nd, 2013
Nvidia R&D chief sketches road to chip stacks
Low-cost organic substrates paired with new I/O techniques represent the best path to 3-D chip stacks, said Nvidia’s chief scientist.
Send to a friend

The company may experiment with such techniques as early as next year in preparation for Volta, its graphics processor slated for 2015.

In a wide-ranging interview, William Dally pooh-poohed the need for cache-coherent memory between CPUs and GPUs being developed by rival AMD. Dally also underscored the rising importance of graphics in computational photography and exascale computing. Chip stacking is increasingly seen as an alternative to moving to the next semiconductor node at a time when process technology is providing less bang for the buck.

It used to be the latest node was critically important,” said Dally, who also serves as Nvidia’s vice president of R&D. “When Dennard scaling was in effect, if you were a node behind you were down a factor of three and basically screwed,” he said. “Now the difference between 28 and 20 nm is probably like 20 to 25 percent,Dally said. “That means to me process doesn't matter that much anymore, so if we are clever about architecture and circuit design, we can make up for the fact that we have competitors that are a node ahead,” he said referring to archrival Intel.

One of the clever architectures engineers in Nvidia’s labs are working on is a ground reference signaling scheme geared for future system-in-package devices. The approach, still in research, promises links running at less than half a picojoule per bit at 20 Gbits/second, said Dally.

The I/O could enable organic substrates that are less expensive than silicon interposers but need physically larger links. Nvidia wants individual links that run at 10 Gbits/second per pin, about ten times the rate of links, to enable components with 200 Gbytes/s bandwidth, Dally said.

IBM has used relatively large organic substrates for processor modules measuring as much as 100 mm on a side, Dally said. He sees the substrates used in 2.5-D stacks where a graphics die is laid next to a DRAM stack. Graphics chips generate too much heat to be stacked vertically with memories, and such stacks face relatively high costs and low yields, he added.

To read more: http://www.eetimes.com/



Sep 17th
Sep 11th
Sep 11th
Sep 11th
Sep 11th
©2007 Yole Developpement All rights reserved                  Disclaimer | Legal notice | To advertise
Yole Développement: Le Quartz, 75 cours Emile Zola, 69100 Villeurbanne, France. TEL: (33) 472 83 01 80 FAX: (33) 472 83 01 83 E-Mail: info @yole.fr