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Jun 17th, 2014
Omnivision CMOS imaging: a closer look
At the recent image sensors conference in London Dr. Howard Rhodes, CTO of Omnivision, gave a keynote entitled “The Future of CMOS Imaging”. I-Micronews thought it was worth… A closer look.
Omnivision, headquartered in Santa Clara, was founded in 1995. Since then it has shipped 4.3B sensors and in 2013 shipped 2.25MM sensors per day.
Timeline for pixel shrink and MP devices
Their latest “PureCelTM” technology has higher quantum efficiency, QE (more light per photon being used), better signal to noise ratio (SNR10) , better color filter technology and better low light sensitivity.
Of special interest are Rhodes comments on “stacked CIS” which he calls “replacing the BSI Si substrate with logic”. This is the repartitioning into a 3D stack that we have been waiting for since Toshiba started using backside TSV in 2008, and is similar to what Sony announced last summer (more info here).
Their roadmap shows Omnivision moving from wafer bonding with simple oxide bonding to “hybrid bond stacking with simultaneous bonding of oxide and Cu contacts to 3 wafer stacking where sensors, ISP and memory are fabricated separated and stacked.
Wafer stacking evolution
Initial reliability testing shows no failures for these stacked chip structures.
Initial reliability on hybrid bonded devices
In fact, Omnivision is now showing “hybrid stacking” as one of the key innovations in CMOS image sensing since its inception.
Gen 1 “Oxide-oxide” bonding is the technology Sony licensed from Ziptronix in 2011 (more info here) and accused TSMC and Omnivision of patent infringement over (more info here).
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