Here is an article from Deepak Sekar, Chief Scientist of MonolithIC 3D Inc. He presents innovative approaches developed by Toshiba, Samsung, Hynix and Micron for polysilicon-based monolithic 3D flash memories as well as his company's monocrystalline silicon solution.

You can argue about when NAND flash scaling will end. Some people say two years, others say five. However, there is little argument that a monolithic 3D solution is required when conventional NAND flash scaling ends. Figure 1 shows Monolithic 3D NAND flash memory approaches pursued by Toshiba, Samsung, Hynix and Macronix.
 
The key points to note are:

• Lithography steps for patterning multiple memory layers are shared, which lowers cost.
• Polysilicon is used as the channel material for transistors.
• To be cost-competitive with scaled 2D NAND flash memory, aspect ratios to be etched and filled are often 50:1 or higher. For future generations, aspect ratios need to be increased further!

For more details, please read my old blog post: Looking beyond lithography. As you can imagine, polysilicon transistors and high aspect ratios pose significant challenges. Polysilicon has 6x lower mobility, higher sub-threshold slope and significantly larger variability than single crystal silicon, which makes 2 bits/cell and 3 bits/cell difficult. High aspect ratios are problematic to manufacture and yield too. 

Fig 1: Today's polysilicon-based Monolithic 3D NAND Flash Memories

The questions to ask are therefore: Can we build 3D NAND flash memories with single crystal silicon instead of polysilicon? In addition, can we use low aspect ratios and still have cost-competitive products? I will now describe MonolithIC 3D Inc.’s technology, where both these important problems are solved. We were awarded fundamental patent coverage on this technology just a few months back.

Fig 2: The Ion-Cut process can provide stacked single crystal silicon at low thermal budget.

Ion-cut, the technology used for manufacturing all SOI wafers nowadays, can provide stacked single-crystal silicon at low thermal budgets. Its shown in Figure 2. Ion-cut involves bonding a hydrogen implanted top layer wafer onto a bottom layer wafer, cleaving the bonded stack at its hydrogen implant plane and later polishing the surface. This process was invented in the early 1990s at CEA -LETI and has been in production since the late 1990s.The process costs around $60 per layer of memory, which is affordable. Ion-cut will become a public-domain technology in 2012, when its basic patent expires. For more cost information on ion-cut, please see my old blog post: How much does ion-cut cost?
 
To read the full article, please go on: http://www.monolithic3d.com/2/post/2011/12/where-is-the-nand-flash-industry-heading-and-monolithic-3d-incs-solution.html