To download the latest issue
Apr 2nd, 2012
PTI began volume shipments of ultra-fine pitch bumps for flip chip assembly
Driving for form factor, high performance and cost effective applications, conventional wire-bond PoP, PiP or SiP packages can not completely satisfy such demand. Therefore, MPS-C2 technology is the key to apply for new territory application. PTI has obtained the license from IBM for the MPS-C2 (Metal Post Solder-Chip Connection) technology and will begin the mass production in December2011.
PTI is now co-working with Via Telecom toward MPS-C2 technology. With smaller profile, better electrical performance and ultra-fine pitch, MPS-C2 technology can provide good solution to make bumps on chip pads with Cu Post and Sn/Ag solder. The bumps are formed on Aluminum pads straightly by wafer plating process , and bumps can be connected to organic substrate’s Cu pads by normal SMT reflow process. The Cu post portion will not melt to keep the standoff - height for better reliability. MPS-C2 is easy for system level design and it could be produced with excellent thermal and electrical performance. Few SBT layer, no RDL (Re-distribution) required and high productivity mass reflow FC assembly process can let MPS-C2 achieve the cost- effectiveness. PTI began volume shipments of MPS-C2 with peripheral , in-line 50 um pitch starting from December 2011 and offered the most competitive quotation to our own customers.
As the largest memory IC package and test manufacturing service provider in the world, PTI continuously establish closer alliance with Greatek to strengthen our Logic business. To keep on growing, PTI qualified 300mm copper pillar bumping, copper RDL, and WLCSP packaging in 2011 and dedicated on delivering the next generation of IC integration solutions. PTI promises to keep investing and providing the best package solutions for customers’ varied requirements.
More ADVANCED PACKAGING news