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Jul 3rd, 2013
Paradigm changes in 3D-IC manufacturing
The process flows applied for real product manufacturing are quite different from the process flows initially proposed for a universal 3D IC.
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Successful 3D-IC prototypes have been demonstrated for many different devices. However, while for some applications 3D-IC architectures have been smoothly integrated into products despite their technical complexity and the omnipresent cost pressure, for other products there seems to be a long list of issues (cost, yield, thermal issues, lack of standards, lack of design tools, etc.) that prevents adoption of 3D-IC integration in the near future.

Common wisdom is that a technical innovation is first introduced for high-performance, high-margin applications, for which the performance gain can bear the additional cost. As the technology becomes more mature, costs are reduced and an increasing number of applications adopt the new technology. A good example of this in the semiconductor industry is flip chip bumping. However, if we look at 3D ICs the situation is not so clear. While it is true that some "cost does not matter" applications in the science, military or medical field use 3D stacking, many high-end devices (most notably CPUs) do not yet use 3D stacking. However, some of the lowest-cost devices in our industry such as light emitting diodes (LEDs), micro-electromechanical systems (MEMS) and image sensors have successfully implemented 3D-IC technology.

3D integration can provide many benefits, but only where it can prove to be a sustainable innovation. TSV and 3D chip stacking have been successfully implemented for devices like FPGAs and image sensors, where 3D IC was a means to improve the sales critical parameters of the devices. Its implementation in high-volume manufacturing occurred despite high technical complexity and the omnipresent cost pressure, which is compounded for low-cost devices. Innovation theory suggests that once a new technology has been established for one product, it can be adopted very rapidly by other products.

The process flows applied for real product manufacturing are quite different from the process flows initially proposed for a universal 3D IC. Chip manufacturing and packaging process flows have since been concurrently optimized. C4 bumps are generally manufactured as late as possible in the overall manufacturing process. Thin-wafer processing is a key competence, but in many cases thin-wafer handling after debonding has been eliminated by either overmolding or wafer bonding to another device wafer prior to debonding. Image sensors apply the most radical concept of W2W stacking, which allows reduced manufacturing costs due to bump-less integration and ultra-shallow TSVs. 3D ICs based on W2W integration is a reality.


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