The successful progression of three-dimensional (3-D) integration on multi-level chip designs has enabled the evolution of smaller, faster and smarter devices.
Consumer demand for multifunctional electronic gadgets with reduced form factor has therefore greatly stimulated 3-D integration for the past several years. A key driver for 3-D device integrat ions chemes has been the realization of through-chip communication between multiple vertically stacked layers using through-silicon via (TSV) technology. The fabrication of TSVs, however, is not trivial and involves a series of processes mainly concerning wafer thinning, deep reactive ion etching, dielectric deposition, and electroplating of the actual through-via metal interconnection. Currently, mostly sol id Copper (Cu) via structures are employed in TSV interconnects.
To read the complete article, please click here
To register to 3D Packaging magazines, please click here