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Oct 3rd, 2012
Qualcomm integrates Wide IO Memory onto 28 nm logic chip
At the recent IMAPS meeting in San Diego ( 45th Int Symp on Microelectronics) Guo and co-workers at Qualcomm reported on the stacking of a two chip wide IO memory stack onto a 28 nm logic device.
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Guo notes that while current HVM stacking technologies such as PoP (package-on-package) provide adequate connection between dies for current applications, since the die to die connections go through the substrate, as the communication rate goes up a good portion of the power gets consumed by the connections. In a 3D stack with TSV this power loss can be reduced significantly. In addition to these power loss reductions, if system memory can be stacked on the back of a logic die there will be no need to assemble separate memory on a mother board which will thus reduce the size of the mobile device.

Their 28 nm logic wafers were fabricated in an unnamed logic foundry. The 6 µm diameter TSV on the logic chip were formed via middle, before M1, connecting to the first of 7 copper/low K levels. After bonding to a temporary carrier vias are revealed with a final Si thickness of 50 µm. Backside pads are then created to match the pattern required by the wide IO memory.
The 2 chip memory cube was fabricated by unnamed memory vendor. The microbump array has 4 channels each with 300 µbumps on 40 µm pitch. The bottom memory die has TSV while the top die does not. 

Qualcomm wide IO memory cube on 28 nm logic

They examined two process flows for shipping the the thinned wafer to the OSAT (1) on the carrier before demounting or (2) on a film frame after demounting. In process flow 1 carrier demount at the OSAT needs to be compatibe with the carrier mounting at the foundry. This process flow allows attachment of the memory cube to the logic die before attachment to the substrate. Process flow 2 does not allow such a sequence and necessitates attachment of the logic die to the substrate and then the memory cube to the backside of the logic die.

After optimizing the TSV formation process they found that a KOZ (keep out zone) of 5 µm was adaquate for maintaining a negligable device performance shift. TSV/ubump chain resistance showed a tight distribution.  They found no degredation to the 28 nm BEOL occurred after logic wafer front side fabrication.
The memory in the stack was verified post assembly and they were able to verify integrity of the TSV and u bumps. 
3D X-ray tomography was used to characterize the TSV and microbumps are clearly visable by this technology.

X-ray image of memory stack on logic

Qualcomm concludes that “ there is no technical show stopper for this technology to be implemented into wireless products” although they admit that “ high yield for both the memory cubes and logic to memory stacking is critical…[and] adoption of this disruptive new technology will depend on …a compelling technical and business value proposition which cannot be attained by extending current technical solutions.”



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