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Oct 9th, 2012
SPTS to develop new TSV isolation materials for 3DIC applications with Fraunhofer IZM
SPTS Technologies, a supplier of advanced wafer processing solutions for the global semiconductor industry and related markets, announced that it has signed a JDP Program with ASSID from Fraunhofer-IZM to research sub-175ºC dielectric films in through silicon vias (TSV) for 3D-IC packaging. The program will use 300mm APM plasma enhanced chemical vapor deposition (PECVD) modules installed on a Versalis® platform alongside SPTS etch chambers in the All Silicon System Integration Dresden (ASSID) centre in Dresden, Germany.
ASSID was set up in 2010, to develop 3D integration technologies on 300mm wafers, enabling leading device manufacturers to apply 3D-IC technology in volume production. By integrating the PECVD modules with etch processes on a single wafer handler, ASSID uses the Versalis system to optimize process results and reduce capital expenditure for development and pilot production.
The APM offers unique low temperature PECVD processes, targeting via-last TSV applications and via-reveal passivation. Dielectric layers for TSV isolation can be deposited at temperatures below 175°C to provide high sidewall coverage, low stress and proven ‘in-via’ electrical performance. For via-reveal, the APM offers high deposition rate silicon oxide and nitride films, compatible with silicon-on-glass substrates and combining excellent coverage, barrier properties and electrical isolation.
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