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Aug 28th, 2012
 
STATS ChipPAC advances TSV capabilities with the qualification of 300mm middle-end processing and low volume manufacturing
 
Expanded capabilities in mid-end and back-end TSV manufacturing enable increased 2.5D and 3D packaging integration.
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STATS ChipPAC Ltd., a leading semiconductor test and advanced packaging service provider, announced that its Through Silicon Via (TSV) capabilities have achieved a new milestone with the qualification of its 300mm mid-end manufacturing operation and transition to low volume manufacturing.

STATS ChipPAC is firmly engaged with multiple strategic customers on TSV development programs which support the semiconductor industry’s shift to 2.5D and 3D packaging integration for the mobile, wireless connectivity and networking market segments. The Company’s current 3D TSV development and customer qualification activities include devices at the 28nm silicon node, application processors (AP) and graphic processors utilizing TSV for the high performance wide input/output (Wide I/O) memory interface required by higher bandwidth applications for the mobile market.

STATS ChipPAC was one of the first Outsourced Semiconductor Assembly and Test (OSAT) providers to invest in back-end of line (BEOL) manufacturing capabilities for 2.5D and 3D TSV technology on 200mm wafers. The Company’s BEOL services include chip-to-chip and chip-to-wafer assembly with stealth dicing and fine pitch micro-bump bonding down to 40um. Since April 2011, STATS ChipPAC has been rapidly expanding its TSV offering with 300mm mid-end of line (MEOL) processing capabilities.

“The need for higher levels of integration, improved electrical performance, reduced power consumption, faster speed, smaller device sizes and shorter interconnects is forcing a shift to more complex 2.5D and 3D package designs utilizing TSV technology. TSV technology will be a key requirement in the convergence of mobile communication and computing functionality in devices such as smartphones and tablets. This is a trend which is expected to drive rapid growth and adoption of TSV technology,” said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC.

The mid-end TSV process flow occurs between the wafer fabrication and back-end assembly process supporting the advanced manufacturing requirements of 2.5D and 3D packaging including wafer level, flip chip and embedded technologies. STATS ChipPAC’s MEOL assembly services include microbump technology down to 40um, temporary bond/de-bonding, backside via reveal, isolation and metallization. With the early development of its MEOL capability, STATS ChipPAC is well positioned to support the increasingly popular industry model for 2.5D/3D integration of disparate silicon devices at the package level by an OSAT provider.

Dr. Han continued, “During the implementation phase of our mid-end TSV operation, we investigated multiple process options and identified key cost variables that would affect the commercialization of this technology. Our primary focus has been to develop high volume TSV technology capabilities that we can offer to customers at cost points that make TSV a viable solution. We now have mid-end manufacturing capacity in place in Singapore and are actively engaged with multiple strategic customers on the production qualification of 2.5D and 3D packaging designs.”


 
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