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Nov 6th, 2012
STATS ChipPAC’s advanced eWLB provides a versatile integration platform for the 2.5D and 3D technology evolution
eWLB packaging options expanded to include interposer technology, flip chip interconnect and complex 3D System-in-Package configurations.
STATS ChipPAC today announced that its expanded packaging options for advanced embedded Wafer Level Ball Grid Array (eWLB) technology provide a versatile platform for the semiconductor industry's technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D System-in-Package (SiP) configurations.
The advancement of silicon scaling to 14 nanometer (nm) in support of higher performance, higher bandwidth and lower power consumption in portable and mobile devices is pushing the boundaries of emerging packaging technologies to smaller fan-out packaging designs with finer line/spacing as well as improved electrical performance and passive embedded technology capabilities. With its continuous innovation and extensive manufacturing experience in eWLB technology, STATS ChipPAC has established a flexible integration platform for 2.5D and 3D packaging at a lower overall cost with proven solutions that overcome manufacturing challenges pertaining to design, material compatibility and manufacturability in the industry today.
"We have taken the robust capabilities of eWLB and developed a solid integration platform for proven and successful 2.5D and 3D packaging integration. With our advanced eWLB technology we are able to provide our customers with the flexibility to integrate semiconductor die from diverse semiconductor processes and different silicon nodes into a cost effective interposer solution. We have also extended our eWLB capabilities into high-end flip chip Ball Grid Array (fcBGA) packaging to address future technical challenges in flip chip assembly as advanced technology nodes move below 28nm," said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC.
Interposers are used to connect one active die to another in a 2.5D package configuration, enabling very dense interconnection with more effective heat dissipation, improved processing speed and the flexibility to integrate die from different manufacturing sources. While STATS ChipPAC continues to be in the forefront of the development and commercialisation of Through Silicon Via (TSV) as a 2.5D and 3D integration technology, the Company has in parallel developed new eWLB based interposers to support high density interconnection and routing of multiple dies in a proven, low-warpage packaging structure. The simplified materials supply chain and lower overall cost available with an eWLB based interposer provide a strong technology platform and path for customers to transition their devices to more advanced 2.5D and 3D packages.
With the inherent performance and cost advantages of eWLB, STATS ChipPAC is also effectively addressing some of the challenges in high end flip chip applications that require much finer bump pitches, higher input/output (I/O) densities and the elimination of stress on extreme low-k or ultra low-k (ELK/ULK) dielectric structures at advanced silicon wafer nodes. eWLB's fan-out packaging approach with its inherently lower stress, larger pad pitch, and redistribution layer (RDL) allows higher integration and routing density in less metal layers in an fcBGA substrate. The fine line width and spacing capabilities of eWLB provides more flexibility in the package routing design and offers superior electrical performance, enabling the number of layers in the organic substrate of a standard fcBGA device to be reduced.
"We are leveraging our eWLB technology to drive substrate simplification and cost reduction while achieving tighter line/spaces in a range of 2.5D to 3D configurations that deliver product advantages to our customers in terms of higher performance, higher frequencies, higher bandwidth and thinner package profiles. With eWLB we have the flexibility to embed multiple active and passive components in the same wafer level package with a vertical 3D interconnection that can be achieved without the use of TSV," said Dr. Han.
STATS ChipPAC's eWLB PoP solutions are available in either a single or double-sided configuration and provide a flexible integration platform for stacking a wide range of memory packages on top with a final stacked package height below 1.0mm. The number of interconnections between memory and processor can be up to 1024. The double-sided eWLB PoP technology features a flexible redistribution layer that can accommodate multiple active or passive devices in complex 3D SiP structures which enable very thin profiles, increased performance and superior warpage control.
STATS ChipPAC will be presenting the latest advancements in eWLB packaging and test at the International Wafer Level Packaging Conference that is being held from November 5th to 8th, 2012 in San Jose, California.
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