Recent advances in embedded wafer level packaging technology reduce bottom package height to less than 0.3mm for an overall PoP stack height as low as 0.8mm.
STATS ChipPAC Ltd. (“STATS ChipPAC” or the “Company” – SGX-ST: STATSChP), a leading provider of advanced semiconductor packaging and test services, announced a new milestone in reducing Package-on-Package (PoP) height with its ultra thin embedded Wafer Level Ball Grid Array (eWLB) technology. STATS ChipPAC has pursued innovative advances in embedded packaging design methodology, process enhancements and cost structure to deliver eWLB-based PoP solutions with an ultra thin package profile height of 0.3mm.
The industry adoption of PoP as a dominant packaging approach in stacking the logic processor and memory into a single solution for advanced mobile phones and tablets has accelerated the need to drive ultra thin package profiles in this technology. Earlier in 2012, STATS ChipPAC utilised eWLB technology to deliver a 30% height reduction in PoP, reducing the overall stacked package height from the industry standard 1.4mm to 1.0mm. Today, through further innovations in eWLB technology, STATS ChipPAC has achieved a 40% height reduction in the bottom PoP architecture to provide an ultra thin z-height of 0.3mm, thereby providing customers with the advantage of having an overall PoP package height as low as 0.8mm with proven board level reliability.
“The emergence of ultra slim devices that are able to deliver exceptional performance continues to grow across the mobility, consumer and computing markets. Our breakthrough technology achievements in package height reduction, increased performance and reliability with eWLB-based PoP solutions enable packaging solutions that provide a competitive edge to substrate-based PoP solutions while remaining cost effective,” said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC. “We have successfully developed best-in-class, ultra thin PoP solutions below 1.0mm to support the continued success of our leading-edge mobility customers and will continue to extend our innovative technology to attain even smaller form factors in semiconductor packaging technology.”
eWLB provides a robust packaging platform supporting ultra high density interconnection and routing of multiple die in very reliable, low-profile, low-warpage packages that are cost effective solutions for baseband processors, RF transceivers, power management components and application processors. For high performance applications such as smartphones and tablets, eWLB technology delivers fine line width and spacing of less than 10um/10um as well as superior electrical performance, providing more design flexibility and a more significant reduction in size than is possible with printed circuit board (PCB) substrate technology.
Dr. Han continued, “While traditional PoP solutions are widely used in the high-end mobility market, demand is accelerating for ultra thin, cost effective packages that have the flexibility to serve a range of applications from mid-range to low-end mobile phones as well as tablets that require significantly higher processor speeds. While PCB substrate technology limits the interconnection density of a PoP package to 200-300 I/O, eWLB-based PoP solutions can deliver beyond 500 I/O in an overall thinner package with a dense vertical interconnection and wider interface to stack memory packages on the top. As we continue to expand the capabilities of eWLB and demonstrate innovative variations with this packaging platform, we are seeing more designs migrating to this technology.”