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Mar 6th, 2012
STATS ChipPAC's 3D eWLB PoP technology announced
STATS ChipPAC, a leading semiconductor test and advanced packaging service provider, today announced its next-generation three dimensional (3D) embedded Wafer Level Ball Grid Array (eWLB) Package-on-Package (PoP) solutions. This innovative new 3D technology provides an ultra thin package profile height below 1.0mm, a 30% height reduction over the industry standard 1.4mm total stacked package height.
Market demand for advanced, multi-functional portable electronic devices is driving the need for semiconductor packages with higher thermal and electrical performance, increased bandwidth and speed in an ultra thin package profile. PoP has been a successful 3D packaging approach by virtue of the flexibility it offers in combining individual memory and logic packages vertically into a single solution in the industry standard 1.4mm total stacked package height. While current PoP technologies are effective in integrating multiple functions in a small form factor, reaching the next level of packaging bandwidth and performance in more advanced mobile devices drive advancements in the stacked package profile height below 1.0mm as well as tighter substrate line/space capability.
STATS ChipPAC’s eWLB PoP technology offers customers significant performance, cost and height advantages over traditional substrate-based PoP technology. By utilizing eWLB’s fan-out wafer level packaging approach, STATS ChipPAC has been able to reduce the bottom PoP package height to less than 0.5mm. eWLB PoP is available in either a single or double-sided configuration and provides a flexible integration platform for stacking a wide range of memory packages on top with a final stacked package height below 1.0mm.
"With eWLB we are able to offer a next-generation 3D PoP technology that achieves heterogeneous die integration and higher input/output (IO) density in a significantly smaller footprint than is possible today with standard PoP and flip chip technology. The maximum benefits of eWLB PoP can be achieved through a co-design process with our customers to optimize the functional performance of this ultra thin 3D package,” said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC. “This is the thinnest 3D PoP solution available in the industry today and it delivers significant cost and performance advantages for our customers.”
With high-performance and power-efficient capabilities in an inherently small, ultra-thin package profile, eWLB has been a technology enabler for advanced mobile applications such as smartphones, media tablets and cloud computing. STATS ChipPAC has shipped over 200 million eWLB units at a rapidly increasing run rate and is in volume production with a large number of eWLB package architectures including small die, large die, multi-die and multi-layer designs.
“eWLB has proven to be a scalable advanced technology that opens up a number of opportunities for our customers in terms of product design. In addition to mobile applications, there has been a growing interest from customers in computing applications where fanning out the device interconnection using eWLB technology can reduce substrate complexity and costs. eWLB is also well-suited for the microcontroller market where reducing cost and form factor are a priority,” said Hal Lasky, Executive Vice President and Chief Sales Officer, STATS ChipPAC.
STATS ChipPAC will be presenting the latest information on innovative 3D packaging solutions including eWLB, low cost copper column flip chip PoP technology and stacked die integration of RF packages at the IMAPS International Conference and Exhibition on Device Packaging that is being held March 5th – 8th, 2012 in Scottsdale, Arizona.
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