At the recent RTI Architectures for Semiconductor Integration and Packaging (RTI ASIP), Raj Pendse, VP and CMO for STATSChipPAC (SCP) gave an in depth presentation on SCPs thoughts and approach to advanced packaging and 2.5/3D. i-Micronews thought it was worth A Closer Look….

Pendse defined packaging as progressing on three parallel fronts which can be categorized based on the interconnect density exiting the device (IO/mm 2) .  Package level which includes the various modes of 3D stacking (i.e PoP) at ~ 101 IO/mm2 . Wafer level packaging such as fan in and fan out packaging which range from 101 to 102 IO/mm2 and Silicon level packaging including TSV stacked memory on logic etc. with IO density in the range of 103 to 104 .  

Evolution of packaging options by IO density

Memory access time (latency) currently limits compute speeds in most systems. 3D integration with TSv provides the next logical step in reducing CPU – memory access time.

In 3D mobile platforms 3D provides a quantum jump in bandwidth with low battery power

Since die have become more and more dense and PCB have not increased their density very much, the package has had to absorb all the difference in interconnectivity. Pendse proposes that an additional interposer layer may now make economic sense. Certainly an additional layer of dense interposer should be financially beneficial when die sizes approach lithography limits (retical size ~ 25 mm) . 

The interconnect choice between laminate build up [a]  vs fan out package [b] vs 2.5D TSV [c] depends on product requirements for IO density as shown below.

Projected commercial timing is shown below.

OSAT Options in 2.5/3D
When looking at OSAT manufacturing options in 2.5/3D Pendse  sees the OSATS being capable in the mid end and back end processing.

Interposer fabrication can be handled by the foundry or the OSAT depending on the density with 5 um l/s and sub 25um TSV pitch being the transition point. It is also possible that 3rd parties will enter the market space.