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Dec 7th, 2011
 
STMicroelectronics’ TSV middle for advanced 28nm SoC unveiled
 
STMicroelectronics presented its 28nm CMOS platform at the International Electron Devices Meeting (IEDM) in Washington, D.C. Tuesday.
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The technology features ultra-thin-body fully depleted SOI with back-biasing techniques, embedded DRAM, and TSVs to provide wide IO connections to a DDR DRAM. It is based on a gate-first high-k/metal gate transistor technology developed at the IBM Semiconductor Development Alliance (ISDA) in Fishkill, N.Y., and features three threshold voltages to support various performance/power levels.

Fig 1: SEM cross section of TSV with an aspect ratio around 8.5.

“We are moving more toward high-performance applications in the mobile and wireless space, where there is less of a border between high performance and low power,” said program manager Franck Arnaud, who returned to Crolles, France to run the 32/28nm program after spending several years at the Fishkill, N.Y.-based ISDA.

STMicroelectronics has designed a 28nm SoC smartphone application processor that moves to prototyping in the second quarter of next year, he said.

The 28nm platform includes an embedded DRAM technology running at 400MHz, based on a TiN/ZrO2/TiN capacitor. A cell size of 0.08mm2/Mbit support a high memory density, and the decoupled capacitor keeps costs down, he said.

Fig 2: SoC floorplan.


STMicroelectronics is perhaps the first company to support a via middle 3D TSV technology for a SoC process flow. The vias have a diameter of 6um and a depth of 50um, and support 12.8Gb/s of bandwidth through a 512 bit bus running at 200Mhz to a DDR DRAM. There is no performance degradation of the surrounding logic block, which is sensitive to local noise and mechanical stress.

Read the full article on http://semimd.com/blog/2011/12/07/iedm-stmicro-adds-tsvs-edram-to-28nm-soi-cmos

 

 
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