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Feb 3rd, 2010
 
Samsung presents new 3D TSV Packaging Roadmap
 
It is not a secret that Samsung is actively preparing for 3D integration. The korean electronic giant recently updated its packaging roadmap, including recent advancements in the commercialization of 3D TSV interconnects.
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Everything really started on April 2006 and later on April 2007 when Dr Chang-Gyu - Samsung's Hwang President & CEO - announced the company intention to commercialize 3D TSV stacked NAND Flash memory and 3D TSV stacked DRAM memory. 

Talking about 3D silicon integration at that time, Dr Chang even said "we are at the doorstep of the largest shift  in the semiconductor industry ever, one that will dwarf the PC and even the consumer electronics era".

Dr Chang continued saying that "it is generally perceived that sub-25 nanometers is the limit to maximizing the  efficiency of the silicon base". But, Dr. Hwang emphasized that alternate technologies can counter this apparent  dead-end in ultra-fine process technology such as 3D structure technology and 3D stacking technology

 

Since then, much things have happened as the leading semiconductor company re-organized and recentered around 3 major businesses: memories (DRAM, Flash, NVM ..), CMOS image sensors and Logic LSI division. And it considerely impacted the internal organization of the company's R&D program and efforts to commercialize 3D TSV technology.

Finally, the company announced late 2008 that "Via Last" TSV / WLP manufactured at the backside of the chips will be implemented first into CMOS image sensors, with similar approach that Omnivion, Toshiba, Micron Aptina and STMicro did.

On the new roadmap presented above, Samsung clearly show a strong interest for introducing 3D into logic+memory and logic+logic stacking applications. These two last configurations are now the main driving forces to implement 3D into next generation PoP (Package on Package) and SiP (System in Package) applications such as mobile processors, CPU and high performance ASICs.  The main drivers for 3D here are cost and performance.

 

If the company expect to ship next 3D products in the 2012-2013 time frame, challenges are still present and numerous: namely, they include 300mm 3D TSV infrastructure availability, process flow strategy and scenarios selection (Via first / Middle / Last / After Bonding), Test (with the possibility to stack only KGD, build BIST and JTAG features, develop doble-side probe station or contact-less test technologies, use interconnect redondancies) and I/O interfaces specifications (such as design rules for electrical routing, mechanical bonding and thermal dissipation).


 
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