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> ADVANCED PACKAGING: 3D IC, WLP & TSV
> Save the date of Yole's webcast on "Embedded Wafer-Level-Pa...
> ADVANCED PACKAGING: 3D IC, WLP & TSV
Aug 30th, 2010
Save the date of Yole's webcast on "Embedded Wafer-Level-Packaging"
Following the recent release of their new report about Embedded Wafer-Level-Packages (including both FOWLP and embedded die in PCB), Yole Développement is pleased to invite you to a FREE webinar on October 5th, 2010.
Historically, embedded IC package technology is not new at all: several players such as Freescale with its RCP, Infineon with its eWLB and Ibiden for die embedding into PCB laminated substrates have developed dedicated technologies and process IP in this area for years. Benefits of embedded package integration include miniaturization, improvement of electrical and thermal performance, cost reduction and simplification of logistic for OEMs.
Things are moving really fast at the moment as this year, we see both Fan-out wafer level packaging and chip embedding into PCB laminate infrastructures emerging at the same time, ramping to high volume production. Get a better picture of the technologies & their application with our webcast. Jerome Baron will present Yole's latest analysis on Embedded Wafer-Level-Packaging technologies: · on Tuesday October, 5 at 10.00 am, Europe Summer Time (Paris, GMT+02:00) > To Register click here
· on Tuesday October, 5 at 5:30 pm, Europe Summer Time (Paris, GMT+02:00) > To Register click here
Practical details:
- Audio (phone/VoIP) & video broadcast with chat panel discussion possibilities
- Duration: 1 presentation of 20 minutes + 5 minute for Q&A
- Language: English
- Presentation: a copy of presented document will be sent to each registrant Please feel free to contact David Jourdan (jourdan@yole.fr) may you have any further question. Sources :
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