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Jun 24th, 2011
Semprius – Massively parallel pick and place: a closer look
Serial “pick-and-place” assembly operations are well established and used in the packaging of most microelectronic devices.
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Standard “pick-and-place” tools using vacuum collets are not well suited for handling devices smaller than 100µm (Semprius calls these “chiplets”) or devices thinner than ~ 20 µm.  Modern “pick-and-place” tools operate at very high speeds to achieve reasonable process throughput (> 10,000 placements per hour), but this comes at the expense of placement accuracy.  

“Transfer printing” is a new technique, first developed in Professor John Rogers’ group at the University of Illinois, that enables the massively parallel assembly of high performance semiconductor devices onto virtually any substrate material. This technology is being commercialized by Semprius Inc in Durham NC.

In transfer printing, an elastomeric stamp is used to selectively pick-up devices from a source wafer and then prints (places) the devices onto the target substrate. The key enabling technology is the ability to tune the adhesion between an elastomeric stamp and the semiconductor devices.  The process is massively parallel because the stamp can be designed to transfer thousands of discrete devices in a single pick-up and print operation.  For instance if 240 um sq chips are laid out on a wafer at 250 um pitch and they need to be placed onto a new surface at 2 mm pitch then the stamp will be made up so that the stubs on the stamp (see transfer print stamp below) are at 2 mm pitch and therefore pick up chiplets 1, 8, 16 etc. off the wafer  and then come back for chiplets 2, 9, 17 etc.

The devices to be transfer printed must first go through a process to delineate and release them from their source wafer.  This method utilizes the ability to release devices using sacrificial release layers underneath the device layer.  In the case of silicon devices, silicon-on-insulator (SOI) wafers represent a convenient and readily available source wafer.  Circuits are fabricated, using a commercially available SOI CMOS foundry process with a 5 um device silicon layer and a 1 um BOx.

Following the foundry CMOS process, a trench is cut down to the device silicon around the periphery of the device (No metal wiring levels are present in the trench area). An encapsulation layer is then applied to the SOI CMOS source wafer  to protect the ILD and wiring levels during the subsequent BOx etch. The SOI CMOS wafer goes through the etch process to remove the BOx underneath the devices with HF. The devices are now completely free from the handle wafer, but held is place using tethers in the device layer.  The tethers are designed to break or cleave in a controlled manner during transfer printing. Following the sacrificial etch process the encapsulating layer is removed at which points the ICs are ready for transfer-printing.

Below is a schematic illustration of the transfer printing process.  The custom built “printer” aligns the transfer stamp over the source wafer.  The tool consists of a 5-axis (x, y, z, pitch, roll) motion platform which allows the transfer stamp to be moved relative to the source and target substrates.  A camera positioned above the transfer stamp that independently moves (x, y, z) relative to the stamp.  The transfer stamp is transparent and the camera looks through the stamp to align the stamp relative to the source wafer.  The elastomeric transfer stamp is fabricated lithographically from  PDMS cast against a master.

The stamp is aligned and brought into contact with the released devices (a), the stamp is lifted away (b) from the source wafer and the chips attached to the elastomeric stamp break free from the source wafer.  Next,  the populated stamp is aligned to and brought into contact with the target substrate (c) and stamp is lifted from the target substrate such that the devices are transferred to the target substrate (d).  Often a spin-on polymer is used on the target substrate to enhance the yield of the printing process. Next (e), the stamp returns to the source wafer and steps to the next set of devices.  The process then repeats until the target substrate is fully populated with devices. The transfer process is massively parallel, Semprius having shown as many as 5,280 die per transfer operation. 

The figure below depicts shows the placement accuracy measured on a backplane that consists of 46,080 placed chiplets. Transfer printing yields in excess of 99.9% have reportedly been achieved. 

Initial studies indicate that the transfer-printing process has negligible impact on devices fabricated using a 0.6 um CMOS process. Activities are underway to examine devices made using thinner device silicon and more advanced CMOS nodes. 

When asked about potential applications Christopher Bower, Sr Engineer at Semprius indicated that “…for display applications, transfer printing can be used to print high performance driver circuitry. In the concentrated photovoltaics (CPV) industry there is a general trend toward handling ever smaller solar cells. Transfer printing opens to path to large assemblies of precisely positioned microscale high efficiency solar cells. In addition, fanout packaging options such as Infineons eWLB and Freescale’s RCP require pick and place assembly to fabricate the reconstituted device wafers.  With transfer printing, the package designer would be able to consider assembling smaller devices and the improved placement accuracy would allow for interconnections with tighter tolerance and higher yield.”            



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