I’d like to look at the current state of 3D IC (chip) packaging. In particular, let’s look at 3D die-on-die stacking techniques, and a variation called 2.5D die-on-silicon interposer packaging, both of which face their own realities of implementation. 

2.5D multi-die packaging uses passive silicon-based interposers (substrates) to horizontally connect multiple chips, with IC-scale electrical routing between the die. Through-silicon vias (TSVs) within the silicon interposer are used to route power and signals from the underlying substrate (such as a printed-circuit board), through the silicon substrate to the metal layers of the interposer, which then connect to the chips above through microbumps.

Full text from electronic design website here.