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Jun 18th, 2012
Separate the hype from the reality in 3D-ICs
From cameras and flat-panel TVs to IC chip design and even IC transistor design, 3D is the buzzword these days, and authors aren’t always clear about what aspects of 3D they’re really covering.
I’d like to look at the current state of 3D IC (chip) packaging. In particular, let’s look at 3D die-on-die stacking techniques, and a variation called 2.5D die-on-silicon interposer packaging, both of which face their own realities of implementation.
2.5D multi-die packaging uses passive silicon-based interposers (substrates) to horizontally connect multiple chips, with IC-scale electrical routing between the die. Through-silicon vias (TSVs) within the silicon interposer are used to route power and signals from the underlying substrate (such as a printed-circuit board), through the silicon substrate to the metal layers of the interposer, which then connect to the chips above through microbumps.
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