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Mar 13th, 2014
Silicon interposers with Integrated Passive Devices: ultra-miniaturized solution using 2.5D packaging platform
This paper addresses one of the most promising technologies that meets the demand in terms of miniaturization and increased performance. IPDiA has developed a range of silicon interposers which, when combined with Integrated Passive Devices (IPD) and Through Silicon Vias (TSV), offer a new solution to related portable products, implantable medical devices, avionics and defense.
From an applicative point of view, interposers were first imagined to be used as a pure packaging platform dedicated to dies with large I/O number (high density BGA). They have evolved towards 3D structures to meet the demands of CCD imager, mobile phone and consumer applications. Now, an additional range of applications can be reached with the so-called 2.5D interposers. This new approach offers an economic model perfectly adapted to related portable products, implantable medical devices, avionics and defense.
Several types of material can be considered as interposer substrate, each offering intrinsic properties that need to be seriously considered prior to any other considerations. Silicon is one, and is chosen for the following reasons: first, silicon is a stable base substrate that presents a very small CTE (coefficient of thermal expansion) mismatch with attached external ICs. Since the active parts are in fact often made of silicon themselves, the thermo-mechanical stresses encountered during processing and lifetime application are minimized, thereby increasing the reliability. Silicon therefore offers a very good trade-off between thermal conductivity and thickness. It is also perfectly adapted to via or micro-via technology (including via last technology) and provides wider possibilities in terms of pitch, via diameter and via density. Lastly, it enables passive devices to be integrated (IPD technology) and is compatible with ICs and MEMS.
The interposers can be divided into three families. The three structures show the common key advantages of enabling external integration of active dies without their packaging, as well as integration (externally or internally) of passive devices.
- 2D Silicon Interposer:
- 2.5D Silicon Interposer:
Fig. 2: Schematic of IPDiA 2.5D interposer with PICS IPD and external active dies in flip-chip or chip-on-silicon technologies
- 3D interposer:
Fig. 3: Comparison between 2.5D and 3D interposer structures 
Now that some general points about interposers have been described, we will explore what has been developed so far to optimize the performance and density of these devices. For a better understanding of the results presented, the TSV process flow set up by IPDiA R&D experts will first be detailed. Some design rules will then be given, followed by comparison tables and characterizations. The reliability model tested will also be described. Finally, some applicative examples involving interposers will be detailed. The IPD process will not be developed here, however numerous articles are available on the subject , .
TSV key process steps
- Bonding process: temporary wafer bonding carried out on a glass substrate is necessary to make thin wafer handling possible through the next steps at process temperatures up to 250 °C.
- Deep silicon etching: due to the bonding process, silicon etching is made from the back side to the first dielectric on the front side. During this step, the undesirable notching effect at the bottom of the via is minimized and the thickness variations are absorbed, preparing the ground for functional and efficient vias.
- Insulation deposition: an SiO2 layer is deposited to provide the insulation needed between the lateral parts of the vias and the substrate. At this stage, a thickness ratio of 0.25 between the bottom corner and the top plan and a relative permittivity of 5 are measured, which leads us to conclude that conditions are right for the propagation of RF signals through the TSV with limited attenuation.
- Copper via filling and back side metallization: at this stage, both copper via filling and back side metallization (tracks) are carried out. In order to modulate the copper thickness at the bottom of vias while limiting the thickness at the surface, IPDiA developed ‘super-filling’ obtained with electrochemical deposition and pulsed current. The ‘super-filling’ enables to facilitate the final module assembly.
Fig. 4: Schematic view of the via final architecture
Main design rules
Dimensional comparison table
Table 2: Comparison with several substrates of dimensional features
Thermal and thermo-mechanical comparison table
Table 3: Comparison with several substrates of thermal and thermo-mechanical features
Fig. 5a: Dual Via Chain schematic view Fig. 5b: Equivalent electrical schematic
HF results are presented on figure 6. It represents the transmission and reflection of a 250 µm length DVC.
Fig. 6: HR measurement result. Transmission (S21 in blue) and reflection (S11 in red)
The excellent result of this DVC shows a rejection between transmission and reflection of more than 35 dB throughout the frequency range (up to 20 GHz), and a very low loss in transmission, better than 0.35 dB. This performance is obtained thanks to control of the process, particularly with efficient contact between the copper in vias and the first metal layer on the front side, and the insulation of the TSV even on its critical corner in the bottom.
As shown on figure 7 below, we can conclude that the use of HR silicon has consistently reduced conductive loss in DVC of TSV. The high value of resistance introduced by the use of HR substrate makes it less sensitive to noise effect.
Fig. 7: Simulation (dashed line) and measurement (solid line) of extracted TSV π-shape elements. Parallel capacitance and series inductance (left), series resistance (right).
The table below summarizes some of the electrical performance and behavior of IPDiA TSV technology.
Fig. 8: Daisy chain (50 TSV) used for the reliability tests.
Figure 9 shows the electrical results after this thermo-mechanical stress. Preconditioning was made on a full wafer (74 DVC structures) and TMCL reliability tests on ¼ wafer (16 DVC structures).
Fig. 9: Statistic chart and table on DC resistance results after TMCL reliability test
The Normal distribution of DC resistance on full wafer test (blue bar chart) and the cumulative distribution function (red curve) validates a good uniformity on full wafer for TSV chain structure. Note that the TMCL reliability test has been done on a ¼ wafer having the structure with the higher resistance. Moreover the low number of structure induces a non-Normal distribution. However, the low confidence interval on them reveals good uniformity and therefore good process maturity. The small and successive decreases in DC resistance can be interpreted as a crystalline rearrangement of copper introduced by successive cycling. This statistical approach allows us to estimate single TSV resistance to 124 mΩ with a very high accuracy, i.e. error less than 2%.
1/ 2D silicon interposer with IPD for implantable medical devices
In this first example, major improvements have been brought by IPDiA 2D interposer with Integrated Passive Devices to a medical sensor module including RF communication. The module is to be used in an implantable defibrillation system. The main concerns of the customer are miniaturization (size and weight impacts), stability and reliability. As described in the introduction of this article, the silicon not only serves as a redistribution layer but also allows the integration of passive components within the substrate. It enables a great size reduction (35% area saving, figure 11) and a decrease of the total system weight. Fig. 10: RF module for medical application using IPDiA 2D interposer technology  
Fig. 11: Comparison of module area between standard
Additionally, the PICS technology used for integration of the passive components results in very stable high capacitor integration. Finally, IPDiA offers a complete service with its stable flip-chip technology and the silicon-silicon compatibility between the substrate and the active dies meets the customer's demand in terms of reliability.
2/ 2D silicon interposers with IPD for vision care devices
The finale application of this second example is linked to the medical field, more precisely to preventive treatment for vision care. The first essential advantage IPDiA has brought forward is miniaturization of the final device in x, y and z axes. But IPDiA has also shown its ability to adapt its technology to the customer’s product environment and has developed a module with four 2D silicon interposers including IPD and active components, the complete system being mounted on a 100 µm thick flexible organic substrate.
Fig. 12: Top view of IPDiA 2D interposer with active dies
3/ 2.5D silicon interposer with IPD for Aerospace
The third example implies integrated passive devices with TSV 2.5D interposer combined with a 3D packaging technology, suitable for motor control in aerospace domain. This time, miniaturization and decrease of the total weight of the device is optimized thanks to the combination of IPD, TSV and 3D packing. Reliability is once again achieved by the silicon-silicon compatibility. IPDiA finalizes the complete module by using a stack die technology on the 2.5D interposer.
Fig. 13: Motor controller device for avionic application
Fig. 14: 2.5D interposer with PICS IPD and external active dies
The work on the TSV process optimization has been led in collaboration with CEA-Leti and was part of the PRIIM project funded by OSEO.
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