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Mar 28th, 2012
 
Synopsis unveils its EDA solution for 3DIC integration
 
Synopsys, Inc., a world leader in software and IP for semiconductor design, verification and manufacturing, today unveiled its initiative to accelerate the design of stacked multiple-die silicon systems using 3D-IC integration to meet the requirements of faster and smaller electronic products that consume less power.
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As part of its 3D-IC initiative, Synopsys is working closely with leading IC design and manufacturing companies to deliver a comprehensive EDA solution, including enhanced versions of its IC implementation and circuit simulation products.

3D-IC technology complements conventional transistor scaling to enable designers to achieve higher levels of integration by allowing multiple die to be stacked vertically, or in a side-by-side "2.5D" configuration on a silicon interposer. 3D-IC integration uses through-silicon via (TSV) technology, an emerging interconnection technology that will replace the traditional wire-bonding process in chip/wafer stacking. The use of TSVs can increase inter-die communication bandwidth, reduce form factor and lower power consumption of stacked multi-die systems.

Synopsys' 3D-IC initiative begins at the semiconductor device level. Multi-die stacks incorporate different materials, often bonded together, with varying coefficients of thermal expansion (CTE). Any temperature change causes material stress due to thermal mismatch, leading to silicon deformation and affecting transistor performance. Furthermore, TSVs, microbumps and other solder bumps produce a permanent stress in the zone around them. Synopsys' Sentaurus Interconnect TCAD tool is used to analyze these effects and to model the TSVs in the die stacks, enabling performance and reliability optimization. Semiconductor companies, such as foundries, use the modeling results to create design rules specific to 3D-IC integration to ensure manufacturability and reliability.

As part of its 3D-IC initiative, Synopsys is delivering a comprehensive EDA solution to enable design for 3D-IC integration:

  • DFTMAX™: design-for-test for stacked die and TSV
  • DesignWare® STAR Memory System®: integrated memory test, diagnostic and repair solution
  • IC Compiler: place-and-route support, including TSV, microbump, silicon interposer redistribution layer (RDL) and signal routing, power mesh creation and interconnect checks
  • StarRC™ Ultra: parasitic extraction support for TSV, microbump, interposer RDL and signal routing metal
  • HSPICE® and CustomSim™ circuit simulation: multi-die interconnect analysis
  • PrimeRail: IR-drop and EM analysis
  • IC Validator: DRC for microbumps and TSVs, LVS connectivity checking between stacked die
  • Galaxy Custom Designer®: specialized custom edits to silicon interposer RDL, signal routing and power mesh
  • Sentaurus Interconnect: thermo-mechanical stress analysis to evaluate the impact of TSVs and microbumps used in multi-die stacks

The Synopsys 3D-IC solution is available now in beta and is expected to be in production in calendar Q2 of 2012. Synopsys' 3D-IC solution will be highlighted at the Synopsys User Group (SNUG) Silicon Valley event on March 26-28, 2012.


 
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