In a paper due to be presented at the 2012 Symposia on VLSI Technology and Circuits in Honolulu, Hawaii, TI researchers were set to show results indicating minimal effect on transistors within 4 microns of TSV placement. The paper that researchers were to present also describes the use of nanobeam diffraction to measure near-TSV silicon strain on fully processed wafers to study the net effect of stressors.

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