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Jun 25th, 2012
TI examines TSV induced stress in 28 nm CMOS: a closer look
At the recent IEEE sponsored VLSI conference in Hawaii, Texas Instruments presented data on TSV induced stress in 28 nm CMOS.
The impact of via-middle Cu TSVs on neighboring devices and overlying low-k interconnect has long been a key concern for integrating TSVs into deep submicron CMOS. The TI researchers used NanoBeam Diffraction (NBD) to measure near-TSV Si strain within fully processed wafers. The electrical behavior of poly-SiON P/NFET transistors were characterized for full thickness wafers at 27 ˚C and 105 ˚C for various orientations and proximities to isolated and arrayed TSVs.
“TI is the only company that I know of to use NanoBean Diffraction to study TSV- induced strain,” said Jeff West, Distinguished Member of the Technical Staff at Texas Instruments. “NanoBean Diffraction enables high resolution in-situ strain measurements of transistors embedded within a fully processed wafer, allowing us to compare the impact of intentionally engineered stressors typically used at this technology node with the impact of nearby TSVs. In the case of TI’s 28 nm CMOS, the TSV-induced stress is made inconsequential by these stressors and the local perturbations resulting from typical layout variation.”
Transistors were evaluated with SiGe and dual etch stop liners (ESLs) to intentionally stress the P/NFETs . Via-middle TSVs were introduced after the contact loop prior to Cu BEOL. Ion was measured at 27 ˚C and 105 ˚C for proximities >4 µm for horizontal, diagonal, and vertical offset N/PFET devices from isolated, 40x50 µm and 35x35 µm pitch TSV arrays.
Device placement relative to isolated and arrayed TSVs
Summary of TSV proximity effects on 28nm CMOS devices at 27˚C
NanoBeam Diffraction measurements of Si strain within 5 µm of TSVs were acquired for samples prepared from fully processed wafers, showing that for proximity >1.5 µm the impact of TSVs is negligible.
Optimization of post-TSV plating anneal to allow CMP removal of extruded Cu prior to applying the overlying BEOL has been shown to be effective for reducing Cu pumping. They explored various TSV plating anneals to minimize the impact of the 10 µm TSVs on the overlying BEOL interconnect.
They found that the impact of TSVs on surrounding Si is tensile (device max operating temp 105 ˚C) but that a tensile etch stop layer (ESL) counters the impact of the TSVs on near-surface Si where devices are present. Also, insertion of compressive shallow trench isolation (STI) between the TSV and device will also act to buffer this impact.
They conclude that “…the electrical properties of N/PFETs between 4 and 16m of TSVs are negligibly impacted (<2.3%) when compared to Ion shifts of 10% from DSL (dual stress liner) boundaries encountered within typical 28 nm CMOS layout. For Wide-IO Memory-Logic interface applications employing a 40x50 µm JEDEC TSV array, ESD and decoupling capacitors which do not contain N/PFETs can be placed immediately adjacent to TSVs such that CMOS logic circuitry does not require placement < 4 um."
“What this paper proves, is the successful integration of TSVs into our 28nm CMOS process flow, and we have done so without negatively affecting the CMOS yield or performance” said Jeff Brighton, project manager of TSV CMOS development at Texas Instruments. “This is a critical enabling step along the road to 3DIC integration.”
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