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Sep 24th, 2013
TSMC and Cadence deliver 3D-IC reference flow for true 3D stacking
New reference flow enhances CoWoS™ (chip-on-wafer-on-substrate) chip design - flow certified using a memory-on-logic design with a 3D stack.
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced that TSMC has collaborated with Cadence to develop a 3D-IC reference flow which features innovative true 3D stacking. The flow, validated on a memory-on-logic design with a 3D stack based on a Wide I/O interface, enables multiple die integration. It incorporates TSMC 3D stacking technology and Cadence® solutions for 3D-IC, including integrated planning tools, a flexible implementation platform, and signoff and electrical/thermal analysis.
“We have worked closely with Cadence to enable true 3D chip development,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “With this new reference flow, our mutual customers can move forward confidently with 3D-IC development, knowing that their Cadence tool flow has been validated in silicon with 3D-IC test vehicles.”
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