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Jun 5th, 2012
TSMC Technology Symposium: a closer look
At the TSMC technology symposium held in April around the country, TSMC reinforced their push into the 2.5/3D and advanced packaging and test arenas while indicating that scaling, while moving forward, is being limited to a single process at the 20 node
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The 2012 TSMC Tech Symp was held around the country in April 2012. They officially introduced reference flow 12.0 which features “…new design capabilities in floorplanning, P&R, and IR-drop and thermal analysis to accommodate multiple process nodes simultaneously, as well as a new design for test methodology for silicon interposer design”. 3DIC which first showed up in reference flow 11 now seems fairly well entrenched in the TSMC roadmap.  In addition, silicon interposers which they also call Chip-on-wafer-on-substrate (CoWoS) are defined as “A silicon interposer design includes multiple dies, logic, memory and/or analog/mixed-signal, integrated side-by-side on a silicon interposer, which is implemented in different technology.”

TSMC Reference Flow 12

We have previously discussed TSMC’s announced move into the packaging arena and it continues to be clear that they intend to offer a design through packaging service to the industry [see “2.5D Interposers: A Closer Look” and “3.5D interposer technology could someday replace PCBs" -- TSMC's Doug Yu”].

In terms of 2.5/3DIC  they now clearly shows only the memory and the package substrate coming from outside TSMC, and TSMC taking the packaged chips through final test, once a stronghold of the OSAT community.

TSMC proposed manufacturing flow for chip-on-wafer-on-substrate ( 2.5D)

In addition, we see major moves into the realm of advanced packaging with offerings such as bumping and chip scale packaging with eutectic bump, leadframe bump, wafer level CSP, bump-on-trace, silicon interposer and fan out WLP either being offered or in development. 

TSMC advanced packaging offerings

It appears that interposers and bump technologies will be available from both the Hsinchu and Tainan sites.

Advanced packaging at TSMC locations

We also see that they are now viewing packaging and test as an integral part of the overall IC development cycle. This appears to be a calculated, major bold play to gain a strong foothold in the IC packaging market. 

TSMC service overview

With Continued Node Shrinks come fewer Optimized processes
Shang-yi Chiang, COO at TSMC, announced that they will offer only one process at the 20 nm node. They  initially planned to offer two 20-nm processes, but they have now determined that there is no noticeable performance difference between the two 20-nm processes because 20-nm linewidths are so small there isn't much room for design rule modifications to obtain optimized performance advantages such as their typical high performance process and a low-power process. AT 28 nm TSMC offers four processes including: a high performance process, a low power process, a low power process with HKMG and a high performance process for mobile applications.

Chiang expects its 20-nm process to be in production next year. In 2015, TSMC wants to commence production at the 14-nm node, which will adopt FinFET 3-D transistors similar to that proposed by Intel [see “The Intel Tri-Gate Transistor structure: a closer look”].
The broad TSMC IC product offering is shown in the chart below.

TSMC IC technology offerings



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