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Apr 24th, 2014
 
TSMC details family of chip stacks
 
TSMC's recent symposium in San Jose described a broad family of 2.5-D and 3-D ICs that exceeded my expectations.
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The company presented its work on chip stacks as one part of a broad overview of its technology portfolio for a North American market that makes up 74% of its foundry business.

The foundry giant currently offers four versions of its 28nm process, a 20nm planar technology, and is ramping up a 16nm FinFET process, said Jack Sun, TSMC's chief technology officer. It will offer a 16FF+ process before July that is GDS compatible with the current 16FF and sports 16% to 18% faster data rates and lower leakage, he said.

Looking further down the road map, Sun said TSMC plans a 10nm FinFET technology, which will be 2.2 times denser than the 16nm node. It also expects to offer risk production of a 7nm FinFET process in 2017. The foundry will spend $10 billion on capital equipment this year, the same capex as 2013.

In chip stacks, TSMC has developed low cost packaging alternatives in addition to its well known Chip on Wafer on Substrate (CoWoS) technology. They aim to serve a wide range of applications that could make 2.5-D/3-D packaging technology a strong third leg of the foundry's capabilities.

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