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Jul 30th, 2014
 
TSMC integrated Fan-Out WLP: a closer look
 
Reports persist that TSMC plans to ramp IC packaging revenues to US $1 billion in 2015 and $2B in 2016. This would make TSMC the 3rd largest packaging company in Taiwan by 2016, trailing only ASE and SPIL.
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At the April TSMC Technology Symposium in San Jose,  they described a wide range of  packaging offerings including  an integrated fan-out wafer level packaging (InFO-WLP) process which will start production by the end of the year and  an InFO PoP configuration which will enable stacking a wire-bonded multi-die package on top of an InFO-WLP. iMicronews thought this was worth…..A closer look.
The TSMC integrated fan out WLP [InFO] claims to be a significantly thinner package with much tighter RDL pitch (i.e 10um) 

TSMC InFO will deliver a 10um RDL pitch

The InFO is shown in cross-section below.

TSMC InFO in cross-section

The larger platforms can actually hold multiple chips. While the 8 x 8mm2 platform is targeted at Rf and WiFi chips and the mid sized platform (15 x 15mm2) is targeted at application processor  and baseband chips, the larger 25 x 25mm2 platform could also function for GPU and networking applications. 

InFO should be suitable for many portable applications

TSMC authors report that InFO-WLP provides distinct advantages over FC ball grid array (FC-BGA) packaging since passive devices such as inductors and capacitors can be formed over molding compound for lower substrate loss and higher electrical performance and the smaller form factor leads to better thermal behavior and hence a lower operating temperature for the same power budget, or alternatively, faster circuit operation for the same temperature profile as FC-BGA [1].
In InFO-WLP, copper interconnects, known as PPI, are formed over the exposed on-chip aluminum pads. PPI over the fan-out area can be used to make high performance passive components such as inductors and capacitors.

Fan-out inductors fabricated in InFO-WLP benefit from the lower parasitic resistance of thicker copper traces and the lower capacitance and substrate loss with molding compound, compared to on-chip inductors built over silicon substrate. For a 3.3 nH inductor, we achieve a peak quality factor (Q) of 42 compared to on-chip Q of 12 for 65 nm CMOS. Inductor proximity to molding compound improves Q factor due to lower loss tangent, with inductor directly over molding compound showing the best performance. 

Comparison of InFO WLP to on Die Inductors (ref 1)

TSMC also compared InFO-WLP to a multi-chip FC-BGA package [a package size of 8x8 mm2, with one baseband chip of size 5x5 mm2, two smaller chips of size 2x1.25 mm2, ambient temperature of 25 ˚C, and total power of 2 W consistent with a typical mobile sub-system.
InFO-WLP’s clearly shows superior thermal performance. Elimination of the substrate layer in InFO-WLP reduces both form factor and chip-to-board thermal path. Also reduced die separation in InFO-WLP improves lateral heat spreading. Overall, thermal resistance of InFO-WLP technology is about 14% better than conventional MCM (28.0 versus 32.5 C/W). Here, the difference in thermal resistance translates to a 9.0 ˚C reduction in maximum temperature.

Thermal Performance of InFO WLP to FC BGA MCM (ref 1)

Millimeter wave systems at 60 GHz have drawn attention in applications from high gigabit-per-second data rate transmission. It enables high-definition video streaming and fast file transfer applications.

LTCC and PCB substrate are currently used for integration of mm-wave antenna with RF chip but there are power consumption issues. The high power dissipation results from interconnect losses from chip to antenna through bumps or balls.

The use of InFO WLP for wide bandwidth patch antennas is supported by the low dielectric constant and thick substrate of the InFO [2].  The required  57-64GHz, can be achieved with mold compound (MC) dielectric constant of 4 and MC thickness, h2, of 300μm as depicted in the figure below. It consists of two RDLs sandwiching mold compound. One is for patch radiator with the size of w × l = 890 × 1020 μm2 on the top of MC and the other one is for feeding structure embedded in the polymer on the bottom of MC.

TSMC Patch Antenna Structure (ref 2)

In table 1 (below) we see that the required PA output power for FC on substrate is 14.5mW vs 11.7 for InFO or a 19% power savings.

Generally, the less parasitic effect is, the lower the loss of interconnect is. The figure on the right, below shows the inductance and capacitance of a lumped circuit model corresponding to different packages. It is clearly seen that fan-out package using copper vias can have less parasitic effect. Compared with C4 bumps, it has 70 % reduction in inductance and 73 % reduction in capacitance. This can address that the loss of fan-out package is lower than that of BGA or bumps on LTCC substrate. 

Comparison of InFO to FC and BGA

References:
[1] CC Liu et. al., “High Performance Integrated Fan-Out Wafer Level Packaging (InFO-WLP): Technology and System Integation”, IEEE IEDM, 2012.
[2] CH Tsai et. al., “Area Array Integrated Fan Out Wafer Level Packaging (InFO_WLP) for Millimeter Wave System Applications” IEEE IEDM, 2013.

 

 
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