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Home  >  ADVANCED PACKAGING: 3D IC, WLP & TSV  > Tessera & Nanium Signs Packaging Technology Licensing Agree...
  >  ADVANCED PACKAGING: 3D IC, WLP & TSV
Feb 19th, 2010
 
Tessera & Nanium Signs Packaging Technology Licensing Agreement
 
Tessera and Nanium, Formerly Qimonda Portugal, Sign Packaging Technology Licensing Agreement for DRAM and Other Semiconductor Devices.
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Tessera Technologies announced that its semiconductor packaging subsidiary, Tessera, Inc., has signed a technology licensing agreement with Nanium, S.A. Nanium, formerly known as Qimonda Portugal, previously was the largest semiconductor packaging assembly and test operation within Qimonda. Nanium has now reorganized as an independent company and will focus on providing assembly and test services for the DRAM memory market and other semiconductor products. Products manufactured by Nanium will be incorporated into computers, servers and various electronic devices such as MP3 players, mobile phones, photographic cameras and game consoles. The initial term of the license agreement runs through the end of 2017.

"Our packaging technologies are foundational elements for the DRAM industry, and will be for many years," said Henry R. Nothhaft, chairman and chief executive officer, Tessera. "In addition to licensing Tessera's innovative chip scale packaging technologies, Nanium has licensed a broad range of Tessera's packaging portfolio. As a result, it will be able to offer its customers an extensive variety of Tessera-enabled packages and technologies to fit their needs, including flip chip, stacked-die, and stacked package configurations."

"Having access to Tessera's packaging technologies will allow us to grow and serve customers in the DRAM market and throughout the semiconductor industry," said Armando Tavares, Nanium's president of the Executive Board. "We can now offer our customers leading edge, licensed technologies to enable their products and businesses."

Under the agreement, Nanium has licensed Tessera's semiconductor packaging technology covering a broad range of chip scale, multi chip and flip chip package types. These technologies include integrated circuit devices packaged in "face-down," "face-up," "stacked-die," "package on package," "system-in-package," and "flip chip" formats, utilizing many different types of materials, including packages using either tape- or laminate-based package substrates.

 

 
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