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Jun 25th, 2013
 
Thermal resistance in 3D chip stacks: A closer look
 
In a recent issue of Electronic Cooling Evan Colgan of IBM examined the thermal resistance of microbump interconnect in 3D chip stacks. iMicronews thought it was worth …A Closer Look
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3D chip stacking with TSV and fine pitch microbump interconnect increases the bandwidth and reducing the latency between the chips but also increases the difficulty of adequately cooling the devices during operation.

With a conventional lid-less chip package the thermal path is through the silicon and through the thermal interface material (TIM) layer to the heat sink. Little heat flows through the wiring layers on chip and the solder bumps into the package substrate.

With a 3D chip stack, the heat from multiple chips is now being removed through the back surface of the top chip and both the BEOL wiring layers and the microbump layer between chips are in the thermal path.  Additionally, the chips that contain TSVs are thinned so that they are less effective at spreading heat from hot spots.

Heat removal paths for (a) single chip package and (b) 3D chip stack

The IBM thermal resistance test vehicle consists of a ceramic substrate, a silicon carrier, and four thermal chips. The thermal chips were joined together with ~ 25μm diameter Pb-free solder microbumps, which had an average height of 16μm after bonding. They were underfilled with a material with thermal conductivity of 0.55 W/m-K. 

 Thermal Test Vehicle (a) schematic cross section; (b) SEM of stack; (c) SEM of  underfill and interconnect

Power was supplied to the heater of the bottom chip of the stack (chip A) and the temperate measured at the various temperature sensors in the chip stack. Chips lower down in the stack, i.e. further from the heat sink, are hotter. Higher temperatures in a zone are believed to be due to variations in the thickness of the TIM layer. The temperature difference between adjacent chips increases as the pitch of the microbumps is increased.

For the underfilled case, subtracting the contribution from the thermal chip (5.5 C-mm2/W) from the average values, thermal resistance of ~25μm diameter Pb-free microbumps at  pitches of 50, 71, and 100μm are 8.0, 15.5, and 19.0 C-mm2/W. For the 50μm pitch case, the thermal conduction from the underfill is roughly equal to that of the microbumps alone.

The chip stack was also modeled using thermal simulation software.  They found that the difference in results from varying the heat loss to the board were insignificant and could not explain the differences in resistances at different layers.  Heat spreading was found to be the dominant factor.  The modeled temperature contours, for the four high chip stack without underfill are roughly consistent with the measured values. At the bottom of the chip stack (chips A & B) the hottest areas are those with the 71 μm and 100 μm pitch microbumps and the temperature distribution is more uniform at the top of the chip stack (chips C & D).

The fact that the measured values are higher than estimates using bulk conductivity values for the solder and underfill is consistent  since the actual values must includes the contribution from the UBM layers on the chips and the intermetallic formation in the Pb-free solder microbumps   as well as voids and grain boundary effects. A typical underfilled C4 layer with 200μm pitch and about 70μm height has a thermal resistance of about 100 C-mm2/W. 

 
Measured temp in stack vs. location (a) without underfill ; (b) with underfill (b) 

Modeled temperature contours with the bottom chip powered in a chip stack without underfill.

 

 
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