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Jul 12th, 2012
 
Toray attempts to eliminate material entrapment when using NCFs: a closer look
 
We recently noted that as we move into the era of super high density interconnect with copper pillar bumping and 3DIC, the requirements placed on underfill have required changes in this technology (see "Underfilling in the era of high density / 3D interconnect: a closer look").
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We also have examined the current status molding technologies for such high density interconnect (see “Molding Technologies: A Closer Look”).

At the recent IEEE ECTC conference in San Diego, Toray detailed the use of diamond bit cutting to mechanically prepare a uniform clean surface for chip to chip bonding thus eliminating the issues of polymer or filler entrapment during interconnect and the resulting high resistance connections.

Their 25 μm diameter / 50 μm high bumps consist of  10 μm  Cu pillars and 40 μm Sn-Ag solder cap on a bump pitch of 200 μm. The 55 μm NCF ( 50 wt% filler loaded)  was laminated on the wafer and then the surface was planarized by the bit cutting technique. Such chips were bonded to the mating bottom chip with a 25 μm diameter pad of 3 μm Cu / 2 μm Ni / 0.1 μm Au cap.

Fujitsu first developed this bit cutting technology (1) for their low temp Cu-Cu thermocompression bonding technology (see “Fujitsu low temp copper thermocompression bonding”).


 
Toray NCF bonding with diamond bit cutting

Pre-applied adhesive processes require near zero material entrapment at the bump /pad joint interface.

It is known that after the film is laminated to the electrode surface, any material covering the electrode can be removed chemically or mechanically. CMP is well known to be used to clean these surfaces (2). In this study diamond bit cutting which the authors claim is simpler and cheaper than CMP is used to prepare a clean surface. Such cutting results in a very clean surface.

 
SEM of diamond cut surface

When the top chip and lower chip are joined the temp must be raised slightly to get the NCF to flow. They call this a “sticking process” which serves to  hold the two chips in place. 
 

Toray bonding process flow

Bonding conditions for placement, sticking and joint formation are shown below:

Bonding conditions

In terms of pressure, they found that 100N was too high and resulted in squeezing the solder out between the copper bump and the pad. Chips can be placed and then gang bonded to shorten the manufacturing time.

Effect of pressure on bonding (1) 10N; (2) 100N

 
The joint reliability of the gang bonded sample was evaluated by PCT (pressure cooker test). In the test the samples were kept at 121 ˚C and 100% RH for 168 hrs. Keeping the final “joint forming” (solder melting) time short, i.e 5 sec, limited the formation of Cu/Sn intermetallics and resulted in parts that passed PCT testing.

References:
1. Mizukoshi, “A new Planarization Technique by high precision diamond cutting for packaging,” Proc. SEMI Technology Symposium, 2004, pp. 825-829.
2. Steigerwald, J. M. et al, Chemical Mechanical Planarization of Microelectronic Materials, Wiley-VCH (Veinheim, 2004).

 

 
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