The smaller module has enabled Toshiba to shrink the pixel size of the HEK3 VGA CIS (see Figures 3) by 41% to 2.2 μm x 2.2 μm. Toshiba has shrunk the actual die shown in Figure 3 by only 15% compared to the previous 0.3 megapixel CIS die without TSV, which means that more on-chip image processing circuitry could be implemented.

Taking a look at the basic construction of the Toshiba HEK3 CIS with the TSVs, the front side of the CIS die is completely covered by a glass support plate (see optical image of Figure 4).

The IR filter which is glued on top of this support glass plate partially covers the front side of the CIS die. TSV’s connect the test pads on the front side of die to the copper redistribution layer (RDL) lines on the backside of the die (see X-ray image of Figure 4). Some of the RDL lines connect to the solder balls formed on the back side of the die. Figure 5 shows the HEK3 CIS module construction in cross-section. The TSV’s located at the right left edges of the CIS die are made up of an outer core lined with electroplated copper and two inner cores filled with organic materials, as shown in the cross-section image of a single TSV (see Figure 6). The copper liner of the TSV is isolated from the CIS silicon by a thin CVD insulating layer.

The first organic fill that fills the inner core of the TSV also covers the backside of the CIS die, along with the copper RDL lines. The second organic fill layer partly fills the dimple in the TSV left after the first organic layer. It is well known that there are two anticipated methods for creating TSVs. The first is with an etching process and the second is with laser drilling. It was expected that the high end products, which will use vias with sizes of 10 μm or less and high aspect ratios, will use wafer-process-based technologies.

Examples of such technologies include the following: stepper lithography; wet etching or DRIE; chemical vapor deposition (CVD), chemical mechanical polishing (CMP) in clean rooms with high cleanliness.

In low-end products like CIS, a lower package height is the driver for TSV. As a result, they need a low-cost process that’s more similar to a printed wire board (PCB) process including laser drilling, laminated dielectric film deposition and metal electroplating. The Toshiba TSVs seems to have bucked this trend. The Toshiba TSV is shaped in the form of an inverted “beer glass”. This shape is characteristic of a hole drilled using laser ablation. Toshiba has disclosed in a research paper that vias were drilled using the third harmonic generated (THG), 355 nm wave length, yittrium aluminum garnet (YAG) laser from the back of the wafer [2].

However at the top of the TSV there is a pedestal that connects the TSV to the front side metallization. This pedestal hole is lithographically defined at the top of the TSV (or the bottom of the “beer glass” looking from the backside of the wafer) and etched using a deep reactive ion etching (DRIE) process. However, it is possible that the entire etch process for the creation of the TSV and its pedestal was a DRIE process. TSVs have finally found their way into mainstream products and it looks like we will be able to look back on 2008 as the year of the TSV after all.

CONTACT

Rajesh Krishnamurthy, Process Analyst in the Technical Intelligence Business Unit at Chipworks Inc.

REFERENCES

1. http://www.toshiba.com/taec/news/press_releases/2007/assp_07_493.jsp
2. Kenji Takahashi et al., “Through silicon via and 3-D wafer/chip stacking technology,” IEEE Symposium on VLSI Circuits Digest of Technical Papers, 2006, 89-92.

More information

Chipworks and Yole Developpement have combined their efforts and in-house expertise to release an exclusive joined report on Toshiba’s latest CMOS image sensor featuring TSV ‘Through Silicon Vias’ interconnects. The new report features three different chapters presenting the market perspectives, a technical analysis and a reverse costing analysis of the first high volume Through Silicon Via implementation. This work is being based on more than 50 high quality tear-down analysis pictures (using TEM, SEM, Optical and X-Ray methods) that Chipworks has recently realized on Toshiba’s lasted TSV / WLP camera module. The reverse costing analysis is based on Yole’s TSV+ Cost Modeling tool, a cost model that the company has been developing in strong interaction with 3DIC equipment and semiconductor players since 2 years now. The new report is available now for purchase from either company for the same price. For more information, please contact David Jourdan at jourdan@yole.fr or Steve Brown at sbrown@chipworks.com.