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Oct 17th, 2012
UMC ready to compete in 2.5/3D foundry space: a closer look
At the recent Semicon Taiwan conference and exhibition Kurt Huang, Dir of Marketing for UMC gave a presentation entitled “Foundry TSV Enablement For 2.5D/3D Chip Stacking”.
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Their presentation made it clear that they will be ready to compete with TSMC in the foundry interposer and 3D stacking business. Looking at the ecosystem they see several work flow models and point out that each OSAT / foundry will have their own capabilities and preferences and that work flow optimization may depend on BOM cost, stack recipe and test strategy.                                                

Ecosystem work flow models

UMC indicates that their foundry design rules for interposer fabrication are ready to go with product level packaging & testing and reliability assessment scheduled for completion in 4Q 2012. 

UMC groundrules and document status

UMC will use “ …mainstream, via-middle Cu TSV technology. RDL on the interposer wil use their 65nm-generation BEOL technology and 3D will initiate with  28nm CMOS logic. After 28nm they envision “.. TSV for 3D may come as a standard option for foundry CMOS logic at 20nm and beyond”

 Cross sections of UMC Si interposer and 3DIC stack

TSV are formed after CMOS but before contact/metal as shown below:


Insertion of TSV into the process flow

Their TSV formation process flow will follow the following sequence:

Process flow for TSV formation and fill

Typical 3D TSV are 6 x 50 and for interposer are 10 x 100 um. KOZ have been determined to be 5 um for 28nm HKMG core device with TSV pitch: JESD229 50/40um.
As specific product examples UMC showed 2.5D solutions by Xilinx and e-Silicon and the 3D wide IO memory stacks of Samsung and Micron.

Commercialization of 2.5 and 3DIC



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