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Oct 24th, 2013
 
Ultra Low Profile Silicon Capacitors (down to 80 µm) applied to Decoupling Applications. Results on ESR/ESL.
 
This paper covers technological advances on ultra low profile silicon capacitors for embedded applications and System in Package modules. It also presents a novel approach to design high density PICS® silicon capacitors to control and optimize their ESR values preserving low intrinsic ESL values that are beneficial for applications at very high frequencies.
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Introduction

As consumers are eager to get the most cutting-edge products, manufacturers have to adapt their technologies and continue to drive innovations to offer the most advanced electronic equipment. Two key features must often be considered for electronic devices: size and performance.

In the case of embedded applications and System in Package modules, not only must the size of the device be optimized in x and y axes, the thickness is also highly important. IPDiA is the 3D Silicon leader providing a full range of silicon capacitors, including some with ultra-low profile - down to 30 µm - developed and offered for decoupling applications with space constraints (memory products like smartcards, memory modules, RFID packages, flash memory cards, etc).

In terms of performance for decoupling applications, the main feature that needs to be improved is the signal integrity of the integrated circuit. On top of the low profile feature, these applications are very demanding in signal integrity and decoupling capacitors are considered to be one of the best solutions in terms of efficiency and cost to reduce the voltage fluctuation. However, decoupling capacitors are not perfect and their performance depends not only on the capacitance but also on the Equivalent Series Resistance (ESR) and on the Equivalent Series Inductance (ESL) [1], [2]. Figure 1 shows the equivalent circuit of a capacitor, taking into account the parasitic effects induced by the ESR and the ESL [3].

 

 

Figure 1: Electrical schematic of a decoupling capacitor

 

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