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Jan 3rd, 2012
Underfilling in the era of high density / 3D interconnect: a closer look
It was 25 years ago that Nakano of Hitachi revealed that flip chip IC mounted in ceramic packages had better reliability when the area surrounding the solder balls was encapsulated with an epoxy “underfill” [1].
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Five years later, Tsukada of IBM Japan published reports that bumped chips could be reliably attached directly to PWB laminate, if underfilled. He concluded that underfill reduced the TCE mismatch between the organic laminate and the silicon IC by mechanically coupling the chip to the substrate and restraining x, y movement between the two interfaces [2].  Within a few years bumped and underfilled die were being used to miniaturize cell phones, pagers, camcorders and other portable products. Since that time the widespread use of bumping technology and the use of underfill have been joined at the hip.

Although assemblers would rather not underfill, due to the reduced throughput caused by capillary underfill flow time and cure time, portable devices continue to be underfilled today due to reliability concerns. The WPB twisting motion which occurs during thermal cycling and solder ball shearing during the drop test are known reliability concerns.

As we move into the era of super high density interconnect with copper pillar bumping and 3DIC, the requirements placed on underfill have required changes in this technology.  i-Micronews felt it was time to take…  A Closer Look.

Several basic underfill processes have evolved through the years. We can basically divide underfills into two major categories, post applied and pre applied.  Post applied underfills include capillary underfills and molded underfills. Preapplied underfills can be further categorized by whether the underfill is applied to the substrate or the wafer.  Capillary underfills can be applied by needle or jett dispense and can be vacuum assisted. Wafer pre applied underfills can be spin on materials or vacuum laminated films. Likewise substrate applied underfill can be applied as a film or from a syringe.  

Underfill technology options

Capillary underfill   
Capillary flow underfill (CUF) was the first technology brought to market for early chip on board and flip chip in package applications . Initial products showed high viscosity, slow flow and  long curing times, but faster flow and faster cure materials were quickly developed by a number of suppliers.

In CUF, a needle dispenses liquid underfill on one or several sides of the die, capillary action pulls the underfill throughout the empty spaces between the die and the substrate and the underfill is then thermally cured. Two dispensing methods can be employed: contact dispensing and underfill jetting .

Jetting results in the ability to achieve tighter component pitch due to the smaller resultant fillet, but even jett dispensing appears limited to ca. 200 µm component gaps.

Pre applied underfill
In pre applied underfilling solder reflow and underfill curing occur in the same process sequence, requiring formulations that are stable at solder reflow temperatures and then are cured at higher temperatures.

No flow underfill applied to substrate
Underfill applied to the substrate, before flip-chip assembly, is usually called NUF for “ no flow underfilling”. NUF is dispensed and cured in the flip-chip bonder during the solder connection process. The underfill acts as flux so it’s unnecessary to flux the substrate or solder bumps. As for all underfills, filler content is important.  Low filler content results in high CTE, which  limits the thermal cycling advantages of the underfill but high filler content prevents bumps from contacting pads on the substrate or results in inclusion  into the solder joint. Each IC must be pressed down through the underfill material, which adds time and cost to the pick and place operation. NUF must also be transparent enough so that alignment marks are visible.  

WUF - Pre applied underfill applied to the bumped wafer
Underfill dispensed at the wafer level, by means of a laminated film or by spin coating , before or after bumping and dicing of the wafer is known as WUF for wafer applied underfill. A WUF process flow would be the most  SMT compatible underfilling process. 

Wafer Applied Underfill

In a WUF lamination process a non conductive film (NCF), usually a epoxy/filler composite, is laminated to the bumped wafer,  the wafer is mounted on flex frame and the wafer diced and mounted on board / package. 

 NCF WUF process flow

Technologies such as FCI’s polymer collar [3] or Lords  wafer level solder brace [4] are not really considered pre applied underfills since although reinforcing the chip/bump interface, such materials do not make contact with the substrate surface.

Molded Underfill
Molded underfill (MUF) is a post applied process using modified epoxy molding compound (EMC) and transfer molding to fill the flip chip gaps and encapsulate the chip at the same time. A 4X increase in throughput vs capillary underfilling has been reported [5]. The flow of MUF between the flip-chip IC and the substrate is usually assisted by vacuum. Molding temperatures are reduced to avoid reaching the bump melting point during the molding process. In order to cope with the trade-off of high filler content for high CTE while still being able to flow under the flip-chip IC, MUF materials are being designed with smaller size fillers. Package warping due to mold material properties is an issue. Molding can also be done at the wafer level [6]. Current MUF technologies are limited to about 200 µm ball pitch. With current materials and equipment MUF does not currently appear to be an option for high density / 3DIC packaging.

Molded underfilling

Although much R&D has occurred on such materials for NUF WUF and MUF, they have not been widely adopted in commercial production yet.

High density interconnect / 3DIC means narrow gaps and tight pitches
On everything from high I/O  single chip packaging to SiP to 3DIC the future is higher density IO pitch whether it be copper pillar bumps or copper-copper  thermo-compression bonding. All of these options will continue to need underfill, but the underfill will be required to be applied  into the new small gap, tight pitch environment. Two main technologies are being developed to alleviate these issues: (a) vacuum assisted underfilling and (b) modification of filler.

Vacuum Assisted Capillary Underfilling for High Density / 3DIC
The use of capillary underfill becomes limited as bump pitches decrease due to flow issues. Voiding is seen during the capillary underfilling of narrow bump gaps/ tight pitches such as in copper pillar bumping or 3DIC stacking. Vacuum assisted underfilling is being developed as a solution to this problem [7]. In this approach, underfill is dispensed around the chip / chip stack under reduced pressure in a vacuum chamber. When the vacuum is released, the lower pressure under the chip / within the chip stack, assists the underfill material in penetrating into the narrow gaps and small pitches between the chips. IBM reports that this is especially necessary for filling 3D stacked chips with narrow gaps [7].

Filler Modification
For fine pitch and narrow gaps, filler size (both max filler particle size and average filler particle size) must be reduced. However, filler size reduction increases underfill viscosity so at a certain point at a given temperature the underfill no longer flows. In the flow data from Namics shown below (all for equal filler loading), UF with 5 µm particle filler is not able to flow in gaps of 25 µm or less, 0.5 µm filler shows acceptable flow even down to 6 µm gaps and 0.05 µm filler shows poor flow even  at 100 µm gaps due to its high viscosity [8]. 

Toray has shown that  NUF with nano-filler, i.e. 50 nm particles , allows for alignment through the UF layer as shown below.

Significant R&D is currently underway to develop WUF for high density and 3DIC stacking since development of a commercially acceptable WUF process flow would make 3D stacking a more SMT friendly process and could be envisioned as having a positive impact on 3DIC process costs [9]. Recent publications, however, indicate that this process is not yet ready for mass production [10]

Thermally enhanced underfills will be required for 3DIC
Another area which needs further development is that of thermally enhanced underfills. Higher density devices are devices in need of better thermal management in general and 3DIC solutions by their very nature exacerbate any thermal issues that are already present. The recent announcement by IBM / 3M that they were  in a joint development program to find thermally enhanced underfills for 3D chip stacking points to the need for thermally enhanced solutions to deal with the increased heat generated in 3D solutions [11] .

[1]. F. Nakano, T. Soga & S. Amagi, “Resin Insertion Effect on Thermal Cycle Resistivity of Flip Chip Mounted LSI Devices”, Proceed. Int. Symp. on Microelectronics, (ISHM), 1987, p. 536

[2]. Y Tsukada, S Tsuchida, Y. Mashimoto, Surface Laminar Circuit Packaging”42nd Electronic Components & Technology Conference (ECTC), San Diego, 1992, p. 22
[3]  D. Luttrull, et. al.,  “Development and Screening of Polymer Collar WLP Candidates for Lead- Free Solder Sphere Technology to Enhance Reliability”, Proceed. Int. Wafer Level Packaging Conf., 2005

[4]  R. Stapleton,” Non-capillary Protection Options for WLCSPs”,   Int Wafer Level Packaging Conf. San Jose, 2008, p. 162

[5] L. Rector et. al., “Transfer Molding Encapsulation of Flip Chip array Packages”, Proceed IMAPS, 2000, p. 260

[6] T. Braun et. al., “Wafer Level Encapsulation - A Transfer Molding Approach to System in Package Generation”, Electronics Packaging Technology Conference, 2002. p. 235.

[7] K. Sakuma, S.Kohara, K.Sueoka, Y. Orii1,M. Kawakami, K. Asai, Y. Hirayama, J. Knickerbocker, “Development of vacuum underfill technology for a 3D chip stack”, J. Micromech. Microeng. 21 (2011) 035024.

[8] T. Fujiki, “New Generation Underfills for Advanced Packaging”,Proceed. of  Int Microsystems Pkging. Assembly and Circuits Conf., Taipei 2010, p. 1-18

[9] S. Katsurayama, H. Suzuki, J.W. Nah, M. Gaynes, C. Feger, “High Performance Wafer Level Underfill Material with High Filler Loading”,   2011 Electronic Components and Technology Conference, p. 370

[10] A. LaManna, K.J. Rebibis, C. Gerets, E. Beyne, “Use of Wafer Applied Underfill for 3D Stacking”, Proceed. 44th Int Symp on Microelectronics ( IMAPS ), Long Beach, 2011, p. 8-16

[11] http://www.i-micronews.com/news/IBM-3M-join-forces-develop-“Silicon-Skyscraper”-closer-look,7529.html



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