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Mar 8th, 2012
 
Vendors aim to jumpstart temporary bonding market
 
3D chips are moving closer to volume production, but there are still challenges with the technology.
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Design issues, test problems, supply chain headaches and cost are still among the challenges to bring 2.5D and 3D chips using through-silicon vias (TSVs) into mass production. But many in the industry blame one set of fab tool technologies — the temporary bonding and debonding gear — as one of the bigger bottlenecks in 3D chip production today.

Cost, immature processes and throughput are among the issues with current temporary bonding and debonding tools. Two leading tool suppliers, EV Group and Suss Microtec, have separately taken steps to solve the problem by rolling out new and high-throughput platforms.

But seeking to change the landscape, Tokyo Electron Ltd. (TEL) has recently entered this tool market. And another new player — Applied Materials Inc. — is looking to shakeup the market and is reportedly readying a new tool, according to sources and analysts.

The temporary bonding/debonding tool business “is still a small market,” said Eric Mounier, an analyst at Yole Développement, a research firm, but “TEL and Applied are willing to enter this market” to get a foothold in the business.

Applied, however, has yet to announce a tool in the arena. A spokeswoman from Applied Materials declined to comment on those reports, saying that “We can’t comment on rumors about entering a market.”

Meanwhile, for some time, MEMS and other niche devices have used temporary bonding/debonding gear. These tools are suitable for the lower-volume MEMS market, but not for semiconductor production, Yole’s Mounier said. “It’s a different business,” he said. Chip makers demand “smaller footprint and higher throughput” tools.

Today’s temporary bonding/debonding steps in the 3D process flow are “very expensive,” added Jerome Baron, business unit manager for advanced packaging at Yole. “It’s a very immature process.”

Leading-edge chip and packaging houses are pushing Applied and TEL to enter the market in hopes of solving these issues. “People say (Applied) is developing a tool,” Baron said. “They are driven by customer demand.”

Needless to say, there is no guarantee that TEL, and reportedly, Applied, will succeed in this tool market. EV Group and Suss are looking to protect their installed base, but the two vendors are under pressure.

Sesh Ramaswami, managing director of strategy for the Silicon Systems Group at Applied, also declined to comment on reports that Applied will enter the business. “It doesn’t mean we’re doing something — or nothing — about it,” Ramaswami said.

Applied is a major player in 3D TSV, where it provides many tools in the arena. Commenting on the current state of the overall 3D chip market, Ramaswami said the business remains in its infancy. “It is still in the early stages. If you look at the players, they are shipping engineering samples. Customer samples are starting at the end of the year. Some production will start in the second half of 2013,” he said.

Changes seen in bonding landscape

There are a number of process steps to make a 3D chip. In the via creation or via processing process, there are five main steps: etch, CVD, PVD, electroplating, and CMP. The overall cost-of-ownership (COO) is declining for the via processing steps, he said.

Temporary bonding/debonding is not ready for prime time (Source: Yole Développement)

In the front-end process, the real bottleneck centers around the temporary bonding/debonding area. Traditional silicon wafers have thicknesses of about 500 micron and so, which can be used to process most mainstream IC devices in a fab. They do not require temporary bonding/debonding gear.

A new class of 3D devices using TSVs will require ultra-thin wafers of 100 micron and below in the production flow. But in  the traditional IC production flow, ultra-thin wafers “are less stable and more vulnerable to stress,” according to Yole. “To address these challenges, as chip thickness is reduced, new processes including temporary bonding technologies will be required for handling such fragile wafers, specifically to support the wafer during back grinding and subsequent post-thinning processes.”

In the temporary bonding/debonding process, a wafer is processed in a fab. Then, the wafer is flipped. A separate carrier wafer with an intermediate layer is temporarily bonded onto the main wafer. Then, the main wafer undergoes a backside thinning process. At that point, the main wafer is debonded from the carrier wafer and cleaned.

In what is seen as a crowded field, the current bonding/debonding equipment suppliers include DoubleCheck, Dynatex, ERS, EV Group, Nitto Denko, Suss, Sysmelec,  Tazmo, TEL, TOK and Yushin. In total, EV Group and Suss combined have about 75 percent share in the temporary bonding/debonding market, according to the firm. This tool business is expected to grow from $64 million in 2011 to $94 million in 2012, according to Yole.

Source: Yole Développement

The average selling price for a temporary bonding/debonding tool is $4 million to $5 million, with throughputs ranging from 10 to 12 wafers an hour, according to Baron and Mounier. The IC industry wants throughputs from 20 to 30 wafers an hour, they said. Temporary bonding/debonding represents 10 percent to 20 percent of the production costs in a 3D TSV line. The goal is to reduce that to between 5 percent to 10 percent, they added.

Providing another insight, Applied’s Ramaswami said temporary bonding/debonding tools are in their infancy. “The bonding equipment is fairly early in their life cycles,” he said. “If you compare 2009 and today, significant progress has been made.”

In any case, the message is clear: The market is screaming for faster machines at a lower cost-of-ownership. “We get the message,” said Paul Lindner, executive technology director for EV Group, a supplier of temporary bonding/debonding and other fab gear. “The price needs to go down. Throughput needs to go up.”

EV Group has installed some tools in various 3D TSV pilot lines, and the company is keeping a close eye on the new entrants in the arena. “In the mainstream 3D chip market, everyone is trying to get a piece of the pie,” Lindner said.

Responding to the throughput issues, EV Group recently rolled out its new equipment platform, dubbed the XT Frame, for its fab tool lines. EV Group’s temporary bonding/debonding system – the EVG 850TB/DB – is the first tool to be built on the XT Frame platform. This enables temporary bonding/debonding at throughputs of 35 to 45 wafers an hour, depending on the application. That’s roughly two to three times faster than previous machines, Lindner said.

Responding to EV Group’s announcement, Suss Microtec last month launched its high-throughput platform, dubbed the XBC300 Gen2. And recently, TEL officially entered the market by rolling out a trio of products. The first product, the Synapse V, uses special-purpose materials to bond wafers to each other. The second tool, Synapse Z, debonds temporarily bonded wafers. And the Synapse S permanently bonds wafers to each other without the use of special materials.

We can alleviate current throughput bottlenecks and increase productivity,” said Joel Barnett, strategic product manager for surface preparation systems at TEL.

TEL declined to comment on the company’s material suppliers. “There are many competing technology solutions,” Barnett said. “The flexibility of the TEL tool sets allows our customers to utilize almost any material of interest to them.”

To read complete article written by Mark LaPedus, please click here.

 

 
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